zl50415 Zarlink Semiconductor, zl50415 Datasheet - Page 81

• Manufacturer Part Number: zl50415
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

14.7.15
CPU Address:h317
Accessed by CPU, serial interface (R/W)
14.7.16
CPU Address:h31C
Accessed by CPU, serial interface (R/W)
14.7.17
Accessed by CPU, serial interface (R/W)
Select which receive queue is used.
Bit [0]: Select Queue 0. If set to one, this queue may be scheduled to CPU port. If set to zero, this queue will be
blocked. If multiple queues are selected, a strict priority will be applied. Q3> Q2> Q1> Q0. Same applies to bits
[3:1]. See QoS Application Note for more information.
Bit [1]: Select Queue 1
Bit [2]: Select Queue 2
Bit [3]: Select Queue 3
Note: Strip priority applies between different selected queues (Q3>Q2>Q1>Q0)
Bit [4]: Enable flush Queue 0
Bit [5]: Enable flush Queue 1
Bit [6]: Enable flush Queue 2
Bit [7]: Enable flush Queue 3
When flush (drop frames) is enable, it starts when queue is too long or entry is too old. A queue is too long when it
reaches WRED thresholds. Queue 0 is not subject to early drop. Packets in queue 0 are dropped only when the
queue is too old. An entry is too old when it is older than the time programmed in the register TX_AGE [5:0]. CPU
can dynamically program this register reading register RQSS [7:4].
14.7.18
CPU Address:h324
Accessed by CPU, serial interface (RO)
INTP_MASK7 – Interrupt Mask for MAC Port 14,15
INTP_MASK12 – Interrupt Mask for MAC Port G1,G2
RQS – Receive Queue Select CPU Address:h323
RQSS – Receive Queue Status
7
FQ3
7
LQ3
6
FQ2
LQ2
5
FQ1
5
LQ1
4
LQ0
4
FQ0
Zarlink Semiconductor Inc.
3
NeQ3
3
SQ3
ZL50418
81
NeQ2
2
SQ2
1
SQ1
NeQ1
0
SQ0
0
NeQ0
Data Sheet