zl50415 Zarlink Semiconductor, zl50415 Datasheet - Page 31

• Manufacturer Part Number: zl50415
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

6.0
6.1
When a frame enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB.
Data is moved in 8-byte granules in conjunction with the scheme for the SRAM interface.
A switch request is sent to the Search Engine. The Search Engine processes the switch request.
A switch response is sent back to the Frame Engine and indicates whether the frame is unicast or multicast and its
destination port or ports. A VLAN table lookup is performed as well.
A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon receiving a
Transmission Scheduling Request, the device will format an entry in the appropriate Transmission Scheduling
Queue (TxSch Q) or Queues. There are 4 TxSch Q for each 10/100 port (and 8 per Gigabit port), one for each
priority. Creation of a queue entry either involves linking a new job to the appropriate linked list if unicast or adding
an entry to a physical queue if multicast.
When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of one of
the TxSch Qs, according to the transmission scheduling algorithm (so as to ensure per-class quality of service).
The unicast linked list and the multicast queue for the same port-class pair are treated as one logical queue. The
older HOL between the two queues goes first. For 10/100 ports multicast queue 0 is associated with unicast queue
0 and multicast queue 1 is associated with unicast queue 2. For Gigabit ports multicast queue 0 is associated with
unicast queue 0, multicast queue 1 with unicast queue 2, multicast queue 2 with unicast queue 4 and multicast
queue 3 with unicast queue 6.
The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the
destination port.
6.2
This section briefly describes the functions of each of the modules of the ZL50418 frame engine.
6.2.1
The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame departure.
The FCB manager is also responsible for enforcing buffer reservations and limits. The default values can be
determined by referring to Chapter 7. In addition, the FCB manager is responsible for buffer aging, and for linking
unicast forwarding jobs to their correct TxSch Q. The buffer aging can be enabled or disabled by the bootstrap pin
and the aging time is defined in register FCBAT.
6.2.2
The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of
frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a switch
request.
6.2.3
The RxDMA arbitrates among switch requests from each Rx interface. It also buffers the first 64 bytes of each
frame for use by the search engine when the switch request has been made.
Data Forwarding Summary
Frame Engine Details
Frame Engine
FCB Manager
Rx Interface
RxDMA
Zarlink Semiconductor Inc.
ZL50418
31
Data Sheet