zl50415 Zarlink Semiconductor, zl50415 Datasheet - Page 16

• Manufacturer Part Number: zl50415
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

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In summary, access to the many internal registers is carried out simply by directly accessing only three registers –
two registers to indicate the address of the desired parameter and one register to read or write a value. Of course,
because there is only one bus master, there can never be any conflict between reading and writing the
configuration registers.
2.3.2
The CPU interface is also responsible for receiving and transmitting standard Ethernet frames to and from the CPU.
To transmit a frame from the CPU
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To receive a frame into the CPU
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In summary, receiving and transmitting frames to and from the CPU is a simple process that uses one direct access
register only.
2.3.3
In addition to standard Ethernet frames described in the preceding section, the CPU is also called upon to handle
special “Control frames,” generated by the ZL50418 and sent to the CPU. These proprietary frames are related to
such tasks as statistics collection, MAC address learning, aging, etc. All Control frames are up to 40 bytes long.
Transmitting and receiving these frames is similar to transmitting and receiving Ethernet frames, except that the
register accessed is the “Control frame data” register (address 111).
Specifically, there are eight types of control frames generated by the CPU and sent to the ZL50418:
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Note: Memory read and write requests by the CPU may include VLAN table, spanning tree, statistic counters and
similar updates.
In addition, there are nine types of Control frames generated by the ZL50418 and sent to the CPU:
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Similarly, to read the value in the register addressed by the two index registers, the “configure data” register
can now simply be read.
The CPU writes a “data frame” register (address 011) with the data it wants to transmit (minimum 64 bytes).
After writing all the data, it then writes the frame size, destination port number, and frame status.
The ZL50418 forwards the Ethernet frame to the desired destination port, no longer distinguishing the fact
that the frame originated from the CPU.
The CPU receives an interrupt when an Ethernet frame is available to be received.
Frame information arrives first in the data frame register. This includes source port number, frame size and
VLAN tag.
The actual data follows the frame information. The CPU uses the frame size information to read the frame
out.
Memory read request
Memory write request
Learn MAC address
Delete MAC address
Search MAC address
Learn IP Multicast address
Delete IP Multicast address
Search IP Multicast address
Interrupt CPU when statistics counter rolls over
Response to memory read request from CPU
Rx/Tx of Standard Ethernet Frames
Control Frames
Zarlink Semiconductor Inc.
ZL50418
16
Data Sheet