zl50415 Zarlink Semiconductor, zl50415 Datasheet - Page 15

• Manufacturer Part Number: zl50415
• Description: Managed 16-port 10/100 M + 2-port 1 G Ethernet Switch
• Manufacturer: Zarlink Semiconductor

2.0
2.1
Two modes are supported in the ZL50418: managed and unmanaged. In managed mode, the ZL50418 uses an 8
or 16 bit CPU interface very similar to the Industry Standard Architecture (ISA) specification. In unmanaged mode,
the ZL50418 has no CPU but can be configured by EEPROM using an I
serial interface otherwise.
2.2
In managed mode, the ZL50418 uses an 8 or 16 bit CPU interface very similar to the ISA bus. The ZL50418 CPU
interface provides for easy and effective management of the switching system. Figure 1 provides an overview of the
CPU interface.
2.3
2.3.1
The ZL50418 has many programmable parameters covering such functions as QoS weights, VLAN control and port
mirroring setup. In managed mode, the CPU interface provides an easy way of configuring these parameters. The
parameters are contained in 8-bit configuration registers. The ZL50418 allows indirect access to these registers, as
follows:
•
•
If operating in 8 bits-interface mode, two “index” registers (addresses 000 and 001) need to be written, to
indicate the desired 8-bit register address. In 16-bit mode, only one register (address 000) needs to be
written for the desired 16-bit register address.
To indirectly configure the register addressed by the two index registers, a “configure data” register (address
010) must be written with the desired 8-bit data.
INDEX REG 1
(Addr = 001)
SYNCHRONOUS
SERIAL
INTERFACE
Management and Configuration
Managed Mode
Register Configuration, Frame Transmission, and Frame Reception
System Configuration
Register Configuration
16 bit internal
address bus
INDEX REG 0
(Addr = 000)
Figure 2 - Overview of the CPU Interface
8 bit
internal data bus
INTERNAL
CONFIGUE
REGISTERS
Zarlink Semiconductor Inc.
(Addr = 010)
DATA REG
CONFIG
ZL50418
15
RECEIVE
FRAME
FIFO
CPU
FRAME DATA REG
2
(Addr = 011)
TRANSMIT
C interface at bootup or via a synchronous
8/16 bit internal
data bus
FRAME
FIFO
CPU
8/16 bit internal
COMMAND
CONTROL
data bus
RECEIVE
FRAME
FIFO
CONTROL
BLOCK REG
COMMAND
TRANSMIT
CONTROL
Data Sheet
1 AND 2
FRAME
FIFO