zl50409 Zarlink Semiconductor, zl50409 Datasheet - Page 84

• Manufacturer Part Number: zl50409
• Description: Managed 9-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.4.6
CPU Address:h305
Accessed by CPU (R/W)
12.3.4.7
CPU Address:h306
Accessed by CPU (R/W)
The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted. (Default 0x00)
12.3.4.8
CPU Address:h310
Accessed by CPU (R/W)
The CPU can dynamically mask the interrupt when it is busy and doesn’t want to be interrupted (Default 0x00)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bit [5]:
Bit [6]:
Bit [7]
-
-
-
-
Bit [0]:
Bit [1]:
Bit [2]:
Bits [6:3]:
Bit [7]:
1: Mask the interrupt
0: Unmask the interrupt (Enable interrupt) (Default)
1: Mask the interrupt
0: Unmask the interrupt (Default)
Bits [7:0]:
MAC5 – CPU MAC address byte 5
INT_MASK0 – Interrupt Mask
INTP_MASK0 – Interrupt Mask for MAC Port 0,1
Port 0 statistic counter wrap around interrupt mask. An Interrupt is generated when a statistic
counter wraps around. Refer to hardware statistic counter for interrupt sources
Port 0 link change mask
Port 0 module detect mask
Reserved
Port 1 statistic counter wrap around interrupt mask. An interrupt is generated when a statistic
counter wraps around. Refer to hardware statistic counter for interrupt sources.
Port 1 link change mask
Port 1 module detect mask
Reserved
CPU frame interrupt. CPU frame buffer has data for CPU to read
Control Command 1 interrupt. Control Command Frame buffer1 has data for CPU to read
Control Command 2 interrupt. Control command Frame buffer2 has data for CPU to read
Reserved
Device Timeout Detected interrupt
Byte 5 (bits [47:40]) of the CPU MAC address (Default 0)
Note: Bits [42:40] are set on a per port basis using MAC01, MAC23, MAC45,
MAC67 registers. For port 9, this register is ignored and MAC9 is used for bits
[47:40].
Zarlink Semiconductor Inc.
ZL50409
84
Data Sheet