zl50409 Zarlink Semiconductor, zl50409 Datasheet - Page 52

• Manufacturer Part Number: zl50409
• Description: Managed 9-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

10.2
10.2.1
MDC is used for the MII Management Interface and clocks data on MDIO. It is generated by the device from
M_CLK and is equal to 500 kHz (M_CLK/100). If a different speed clock other than 50MHz is used on M_CLK, the
USD register must be programmed to reset MDC.
10.2.2
SCL is used for the I2C interface and clocks data on SDA. It is generated by the device from M_CLK and is equal to
50kHz (M_CLK/1000). If a different speed clock other than 50MHz is used on M_CLK, the USD register must be
programmed to reset SCL.
10.2.3
If the RMAC ports are configured in Reverse MII mode, TXCLK and RXCLK are generated from M_CLK and are
equal to M_CLK/2 for 100M mode or M_CLK/20 for 10M mode. M_CLK needs to be a 50 MHz clock in this mode.
If the RMAC ports are configured in Reverse GPSI mode, TXCLK and RXCLK are generated from M_CLK and are
equal to M_CLK/2 for 10M mode. M_CLK needs to be a 20 MHz clock in this mode and USD must be programmed
accordingly.
For the CPU port in serial+MII mode, TXCLK and RXCLK are generated from M_CLK and are equal to M_CLK/2 for
100M mode or M_CLK/20 for 10M mode. M_CLK needs to be a 50MHz clock in this mode.
If the MMAC port is configured in Reverse MII mode, RXCLK is generated from REF_CLK and is equal to
REF_CLK/2 for 100M mode (no support for 10M Reverse MII mode). REF_CLK needs to be a 50 MHz clock in this
mode.
Clock Generation
MDC
SCL
Ethernet Interface Clocks
Zarlink Semiconductor Inc.
ZL50409
52
Data Sheet