zl50409 Zarlink Semiconductor, zl50409 Datasheet - Page 31

• Manufacturer Part Number: zl50409
• Description: Managed 9-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

In summary, in 8/16-bit or serial only mode, receiving and transmitting frames to and from the CPU is a simple
process that uses one direct access register only. In serial mode with MII interface, the CPU will be allowed to
transmit and receive frames using standard IEEE 802.3 Ethernet transmission format.
The details of sending an Ethernet Frame via the CPU interface is described in the Processor Interface Application
Note, ZLAN-26.
3.1.3
In addition to standard Ethernet frames described in the preceding section, the CPU is also called upon to handle
special “Control frames,” generated by the ZL50409 and sent to the CPU. These proprietary frames are related to
such tasks as statistics collection, MAC address learning, and aging, etc… All Control frames are up to 40 bytes
long. Transmitting and receiving these frames is similar to transmitting and receiving Ethernet frames, except that
the register accessed is the “Control frame data” register (address 111).
Specifically, there are the following types of control frames generated by the CPU and sent to the ZL50409:
•
•
•
•
•
•
•
•
•
•
•
Note: Memory read and write requests by the CPU may include all internal memories which include statistic
counters, MAC address control link table and the 2Mbit (256KB) memory block.
In addition, the following types of Control frames are generated by the ZL50409 and sent to the CPU:
•
•
•
•
•
•
•
•
•
The format of the Control Frame is described in the Processor Interface application note, ZLAN-26.
3.2
The I²C interface serves the function of configuring the ZL50409 at boot time. The master is the ZL50409, and the
slave is the EEPROM memory.
The I²C interface uses two bus lines, a serial data line (SDA) and a serial clock line (SCL). The SCL line carries the
control signals that facilitate the transfer of information from EEPROM to the switch. Data transfer is 8-bit serial and
bidirectional, at 50 Kbps. Data transfer is performed between master and slave IC using a request /
acknowledgment style of protocol. The master IC generates the timing signals and terminates data transfer. Figure
6 depicts the data transfer format. The slave address is the memory address of the EEPROM. Refer to “ZL50409
Register Description” on page 61 for I²C address for each register.
Memory read request
Memory write request
Learn Unicast MAC address
Delete Unicast MAC address
Search Unicast MAC address
Learn IP Multicast address
Delete IP Multicast address
Search IP Multicast address
Learn Multicast MAC address
Delete Multicast MAC address
Search Multicast MAC address
Interrupt CPU when statistics counter rolls over
Response to memory read request from CPU
Learn Unicast MAC address
Delete Unicast MAC address
Delete Multicast MAC address
Delete IP Multicast address
Response to search Unicast MAC address request from CPU
Response to search IP Multicast address request from CPU
Response to search Multicast MAC address request from CPU
I
2
C Interface
Control Frames
Zarlink Semiconductor Inc.
ZL50409
31
Data Sheet