zl50409 Zarlink Semiconductor, zl50409 Datasheet

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zl50409

Manufacturer Part Number

zl50409

Description

Managed 9-port 10/100m Ethernet Switch

Manufacturer

Zarlink Semiconductor

Datasheet

1.ZL50409.pdf (135 pages)

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Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Bonase Electronics (HK) Co., Limited

Part Number:

zl50409GD

Manufacturer:

FUJITSU

Quantity:

541

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Features

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•

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Integrated Single-Chip 10/100 Ethernet Switch

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•

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Embedded 2 Mbits (256 KBytes) internal memory

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L2 switching

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VLAN Support

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Eight 10/100 Mbps auto-negotiating Fast

Ethernet (FE) ports with RMII, MII, GPSI,

Reverse MII & Reverse GPSI interface options

One 10/100 Mbps auto-negotiating port with

MII interface option, that can be used as a

WAN uplink or as a 9th port

a 10/100 Mbps Fast Ethernet (FE) CPU port

with Reverse MII interface option

supports up to 4 K byte frames

MAC address self learning, up to 4 K MAC

addresses using internal table

Supports IP Multicast with IGMP snooping, up

to 4 K IP Multicast groups

Supports the following spanning standards

-

-

Supports Ethernet multicasting and

broadcasting and flooding control

Supports port-based VLAN and tagged-based

VLAN (IEEE 802.1Q), up to 4 K VLANs

IEEE 802.1D spanning tree

IEEE 802.1w rapid spanning tree

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

EEPROM

C

U

P

Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved.

8/16-bit

Serial

MII

or

Figure 1 - System Block Diagram

10/100

Quad

PHY

Zarlink Semiconductor Inc.

Ethernet Switch

9-Port 10/100M

RMII / MII / GPSI

ZL50409

Managed 9-Port 10/100M Ethernet Switch

1

•

•

•

•

CPU access supports the following interface

options:

•

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Failover Features

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Rate Control (both ingress and egress)

•

10/100

ZL50409GDC

Quad

Supports both shared VLAN learning (SVL)

and independent VLAN learning (IVL)

8/16-bit parallel and Serial+MII interface in

managed mode

Serial interface in lightly managed mode, or in

unmanaged mode with optional I

interface

Rapid link failure detection using

hardware-generated heartbeat packets

link failover in less than 50 ms

Bandwidth rationing, Bandwidth on demand,

SLA (Service Level Agreement)

PHY

MII

Ordering Information

-40C to +85C

10/100

PHY

208 Pin LBGA

2

C EEPROM

Data Sheet

ZL50409

November 2004

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