zl50409 Zarlink Semiconductor, zl50409 Datasheet - Page 115

• Manufacturer Part Number: zl50409
• Description: Managed 9-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.10.14
CPU Address EBB, EBC
Accessed by CPU (RO)
12.3.10.15
CPU Address EBD
Accessed by CPU (R/W)
12.3.10.16
CPU Address EC0
Accessed by CPU (R/W)
If CPU wants to reset pools again, CPU has to clear bit 5 and then set bit 5.
Note : Before CPU doing so, CPU should set QCTRL (CPU Address EBA) bit 2 and bit 3 to one. After reset the
pools, CPU shall reprogram free granule link list (CPU address EC1, EC2, EC3, EC4, EC5, EC6). Then clear
QCTRL (EBA).
Bits [3:0]:
Bits [7:4]:
Bits [3:0]
Bit [4]
Bit [5]
Bits [7:6]
BMBISTR0, BMBISTR1
BMControl
BUFF_RST
Assign a value that the pool to be reset
0: port 0 pool
1: port 1 pool
2: port 2 pool
3: port 3 pool
4: port 4 pool
5: port 5 pool
6: port 6 pool
7: port 7 pool
8: port MMAC pool
9: shared pool
10: class 1 pool
11: class 2 pool
12: class 3 pool
13: multicast pool
14: cpu pool
15: reserved
If this bit is 1, then all the pools are assigned
Set 1 to reset the pools that are assigned
Reserved
Block Memory redundancy control
0: Use hardware detected value
All others: Overwrite the hardware detected memory swap map
Reserved
Zarlink Semiconductor Inc.
ZL50409
115
Data Sheet