zl50409 Zarlink Semiconductor, zl50409 Datasheet - Page 70

• Manufacturer Part Number: zl50409
• Description: Managed 9-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.2.6
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12.2.7
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12.2.8
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12.3
12.3.1
12.3.1.1
I²C Address 000+n; CPU Address:0000+2n (n = port number)
Accessed by CPU and I²C (R/W)
Port 0 – 7 & 9: (RMAC & MMAC Ports)
Bit [0]:
Bit [1]:
Bit [2]:
Bits [6:3]:
Bit [7]:
Interrupt sources (8 bits)
Address = 5 (read/write)
CPU transmit/receive control frames (8/16 bits)
Address = 6 (read/write)
When CPU writes to this register:
When CPU reads this register:
CPU receive control frames (8/16 bits)
Address = 7 (read only)
When CPU reads this register:
Indirectly Accessed Registers
Interrupt Register
Control Command Frame Buffer1 Access Register
Control Command Frame Buffer2 Access Register
(Group 0 Address) MAC Ports Group
Bit [0]
Bit [1]
Bit [2]
Data is written to the Control Command Frame Receive Buffer
Data is read from the Control Command Frame Transmit Buffer1
Data is read from the Control Command Frame Transmit Buffer2
ECR1Pn: Port n Control Register
CPU frame interrupt
Control Frame 1 interrupt. Control Frame receive buffer1 has data for CPU to read
Control Frame 2 interrupt. Control Frame receive buffer2 has data for CPU to read
Reserved
Device Timeout Detected interrupt
Note: This bit is not self-cleared. After reading, the CPU has to clear the bit writing 0 to it.
Flow Control
0 - Enable (Default)
1 - Disable
Duplex Mode
0 - Full Duplex (Default)
1 - Half Duplex - Only in 10/100 mode
Speed
0 - 100 Mbps (Default)
1 - 10 Mbps
Zarlink Semiconductor Inc.
ZL50409
70
Data Sheet