zl50409 Zarlink Semiconductor, zl50409 Datasheet - Page 104

• Manufacturer Part Number: zl50409
• Description: Managed 9-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.7.10
CPU Address:h609
Accessed by CPU (R/W)
12.3.7.11
CPU Address:h60A
Accessed by CPU (R/W)
12.3.7.12
I²C Address 0FF, CPU Address:h60B
Accessed by CPU and I²C (R/W)
This register is used in unmanaged mode only. Before requesting that the ZL50409 updates the EEPROM device,
the correct checksum needs to be calculated and written into this checksum register.
Bits [5:0]:
Bits [7:6]:
Bit [0]:
Bit [1]:
Bits [7:2]:
Bits [7:0]:
DEVICE Mode
CHECKSUM - EEPROM Checksum
USD – One Micro Second Divider
Divider to get one micro second from M_CLK (only used when not in standard RMII mode)
In a MII or GPSI system, a 50MHz M_CLK may not be available. The system designer can
decide to use another frequency on the M_CLK signal. To compensate for this, this register
is required to be programmed.
For example. If 20MHz is used on M_CLK, to compensate for the difference, this register is
programmed with 20 to provide 1usec for internal reference.
Reserved
Reserved
CPU Interrupt Polarity
0: Negative Polarity
1: Positive Polarity (Default)
Reserved
Checksum content (Default 0)
Zarlink Semiconductor Inc.
ZL50409
104
Data Sheet