zl50409 Zarlink Semiconductor, zl50409 Datasheet - Page 72

• Manufacturer Part Number: zl50409
• Description: Managed 9-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

12.3.1.2
I²C Address: 00A+n; CPU Address:0001+2n (n = port number)
Accessed by CPU and I²C (R/W)
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]
Bit [5]
Bit [5]
Bits [7:6]
ECR2Pn: Port n Control Register
Asymmetric Flow Control Enable.
0 – Disable asymmetric flow control (Default)
1 – Enable Asymmetric flow control
When this bit is set and flow control is on (bit [0] = 0), the device does not send out
flow control frames, but it’s receiver interprets and processes flow control frames.
SS - Spanning tree state (IEEE 802.1D spanning tree protocol)
00 - Blocking:
01 - Listening:
10 - Learning:
11 - Forwarding:
Filter untagged frame
0: Disable (Default)
1: All untagged frames from this port are discarded or follow security option when
security is enable
Filter Tag frame
0: Disable (Default)
1: All tagged frames from this port are discarded or follow security option when
security is enable
Learning Disable
0: Learning is enabled on this port (Default)
1: Learning is disabled on this port
Rate control timer select (RMAC ports only)
0: 10 microsecond refreshing time (Default)
1: 1 millisecond refreshing time
0
Do not change VLAN tag. This overrides PVMAPnn_3 bit [2]. If this bit is set, no
tag will be replaced nor removed.
0: Disable (Default)
1: Enable
Frame is dropped
Frame is dropped
Frame is dropped. Source MAC address is learned.
Frame is forwarded. Source MAC address is learned. (Default)
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ZL50409
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Data Sheet