zl50409 Zarlink Semiconductor, zl50409 Datasheet - Page 118

• Manufacturer Part Number: zl50409
• Description: Managed 9-port 10/100m Ethernet Switch
• Manufacturer: Zarlink Semiconductor

CPU address ECC
Accessed by CPU (RO)
CPU address ECD
Accessed by CPU (RO)
12.3.11
12.3.11.1
CPU Address: hF00
Accessed by CPU (R/W)
Bits [4:0]
Bit [5]
Bits [7:6]
Bits [1:0]
Bits [3:2]
Bit [4]
Bits [7:5]
Bit [0]:
Bit [1]:
Bit [2]:
Bit [3]:
Bit [4]:
Bits [7:5]:
(Group F Address) CPU Access Group
GCR - Global Control Register
Rls_count[6:2]
If 1, then It is multicast packet.
Rls_src_port[1:0[
Rls_src_port[3:2]
Class[1:0]
This release request is from QM directly.
Entries count in release FIFO, 0 means FIFO is empty
Store configuration (Default = 0)
Write ‘1’ followed by ‘0’ to store configuration into external EEPROM
Store configuration and reset (Default = 0)
Write ‘1’ to store configuration into external EEPROM and reset chip
Start BIST (Default = 0)
Write ‘1’ followed by ‘0’ to start the device’s built-in self-test. The result is
found in the DCR register.
Soft Reset (Default = 0)
Write ‘1’ to reset chip
Initialization Completed (Default = 0)
This bit is reserved in unmanaged mode.
In managed mode, the CPU writes this bit with ‘1’ to indicate initialization is
completed and ready to forward packets. The ‘0' to '1' transition will toggle
TSTOUT[2] from low to high.
Reserved
Zarlink Semiconductor Inc.
ZL50409
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Data Sheet