hsp50214a Intersil Corporation, hsp50214a Datasheet - Page 9

• Manufacturer Part Number: hsp50214a
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

a gain error for use in an AGC loop with either the RF/IF or
A/D converter stages (see Figure 8). The AGC loop
includes Input Level Detector, the microprocessor and an
external gain control amplifier (or attenuator). The input
samples are rectified and added to a threshold pro-
grammed via the microprocessor interface, as shown in
Figure 9. The bit weighting of the data path through the
input threshold detector is shown in Figure 10. The thresh-
old is a signed number, so it should be set to the inverse of
the desired input level. The threshold can be set to zero if
the average input level is desired instead of the error. The
sum of the threshold and the absolute value of the input is
accumulated in a 32-bit accumulator. The accumulator can
Without Interpolation, the CIC bypass path exceeds the HB/FIR filter
input sample rate and the CIC filter path will not yield the desired 85dB
dynamic range band width of 500kHz.
5MHz
IN(13:0)
MIN. R = 4
FIGURE 4. STATEMENT OF THE PROBLEM
BYPASS
FILTER
CONTROL WORD 0
CONTROL WORD 1
CIC
FORMAT
INPUT
GAINADJ(2:0)
†
CLKIN
ENI
PROCCLK = 28MHz
MAX. f
(EXCEEDED IN
BYPASS PATH)
HB/FIR FILTER
INTERP
S
FIGURE 3. BLOCK DIAGRAM OF THE INPUT SECTION
= 4MHz
†
CONTROL
LOGIC
(NOT ACHIEVED
WITH CIC FILTER
PATH)
500kHz = 85dB
BANDWIDTH
DETECT
LEVEL
HSP50214A
14
14
INPUT LEVEL DETECTOR
STATUS (0)
NCO
EN
INPUT_MODE
INPUT_FMT
INPUT_THRESH
INTG_MODE
INTG_INTEVAL
18
DELAY 3
DELAY 3
††
INPUT_THRESH
INTG_MODE
INTG_INTEVAL
9
18
handle up to 2
time is controlled by an 18-bit counter. The integration
counter preload (ICPrel) is programmed via the micropro-
cessor interface through Control Word 1. Only the upper 16
bits are programmable. The 2 LSBs are always zero. Con-
trol Word 1, Bits 29-14 are programmed to:
where N is the desired integration period, defined as the
number of input samples to be integrated. N must be a multi-
ple of 4: [0, 4, 8, 12, 16 .... , 2
ICPrel
†
FIGURE 5. BLOCK DIAGRAM OF THE INTERPOLATION
5MHz
8 (0 STUFF) = 40MHz
†
†
3
†
=
†
†
LIMIT
†
N
†
†
4
4
APPROACH
CIC FILTER
†
4
18
R = 10
+
1
samples without overflow. The integration
††
†
Controlled via microprocessor interface.
See NCO Section for more details.
4MHz
BYPASS
HB/FIR FILTER
18
].
†
500kHz = 85dB
BANDWIDTH
(EQ. 1)