hsp50214a Intersil Corporation, hsp50214a Datasheet
hsp50214a
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hsp50214a Summary of contents
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... Copyright HSP50214A Description The HSP50214A Programmable Downconverter converts dig- itized IF data into filtered baseband data which can be pro- cessed Programmable Downconverter (PDC) performs down conver- sion, decimation, narrowband low pass filtering, gain scaling, resampling, and Cartesian to Polar coordinate conversion. ...
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... V CC CLKIN 16 17 GND 18 NC ENI 19 GAINADJ2 20 GAINADJ1 21 GAINADJ0 22 COF 23 24 COFSYNC 25 GND 26 SOF SOFSYNC SYNCIN1 SYNCIN2 30 HSP50214A 120 LEAD MQFP TOP VIEW 2 90 DATARDY 89 OEBH BOUT15 88 BOUT14 BOUT13 84 BOUT12 83 BOUT11 82 BOUT10 81 BOUT9 80 BOUT8 79 GND 78 GND 77 ...
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... AOUT(15:0) O Parallel Output Bus A. Two parallel output modes are available on the HSP50214A. The first is called the Direct Output Port, where the source is selected through Control Word 20 (see the Microproces- sor Write Section) and comes directly from the Output MUX Section (see Output Control Section). ...
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... Multiple Chip Sync Output. Provided for synchronizing multiple parts when CLKIN and PROCCLK are asynchronous. MSYNCO is the synchronization signal between the input section operating under CLKIN and the back end processing operating under PROCCLK. This output sync signal from one part is connected to the MSYNCI signal of all the HSP50214As. MSYNCI I Multiple Chip Sync Input ...
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... PROCESSOR INTERFACE COF NCO COFSYNC (CARRIER TRACKING) SOF SOFSYNC REFCLK MICROPROCESSOR READ/WRITE RD WR CONTROL A(2:0) SECTION C(7:0) FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF THE HSP50214A PROGRAMMABLE DOWNCONVERTER TO OUTPUT FORMATTER AGCOUT AND MICROPROCESSOR INTERFACE 255-TAP PROGRAMMABLE AGC RE-SAMPLER FIR FILTER (DECIMATE ...
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... Output Sections. All of these sections are configured through a microprocessor interface. The HSP50214A has three clock inputs; two are required and one is optional. The input level detector, carrier NCO, and CIC decimating filter sections operate on the rising edge of the input clock, CLKIN ...
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... FIR fil- ter for additional signal conditioning of the FM signal. Digital versions of these formats, ASK and FSK are also readily pro- HSP50214A cessed using the PDC. Just as in the AM modulated case, ASK signals will use 15-bit magnitude output of the Cartesian to Polar Coordinate converter ...
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... PDC’s, these signals can still be controlled independently. In the HSP50214A, the Control Word 25 reset signal has been extended so that the front end reset is 10 CLKIN peri- ods wide and the back end reset is 10 PROCCLK periods wide ...
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... Without Interpolation, the CIC bypass path exceeds the HB/FIR filter input sample rate and the CIC filter path will not yield the desired 85dB dynamic range band width of 500kHz. FIGURE 4. STATEMENT OF THE PROBLEM HSP50214A handle time is controlled by an 18-bit counter. The integration counter preload (ICPrel) is programmed via the micropro- cessor interface through Control Word 1 ...
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... DECIMATE BY 10 AND CIC FILTER; SAMPLE AT RATE R = f’ 85dB DYNAMIC RANGE BANDWIDTH xxxx xxxx xxxx xxxx xxxx O.5MHz 1MHz FIGURE 7. ALIAS PROFILE AND THE 85dB DYNAMIC RANGE BANDWIDTH INPUT FIGURE 8. PROCESSOR BASED EXTERNAL IF AGC HSP50214A ...
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... INPUT GATING IN(13:0) LOGIC † INPUT_THRESHOLD † INTEGRATION_INTERVAL † START † INTEGRATION_MODE CLKIN † Controlled via microprocessor interface. HSP50214A ACCUMULATOR CLKIN “0” 16 COUNTER CONTINUOUS SINGLE FIGURE 9. 11 ADDR(2: PROC ...
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... E) DETECTOR OUTPUT FIGURE 11. SIGNAL PROCESSING WITHIN LEVEL DETECTOR In the HSP50214A, the polarity of the two LSB’s of the inte- gration period pre-load is selectable. If Control Word 27, Bit 23 is set to a logic one, the two LSB’s of the integration period preload are set to logic ones. This allows a power of two to be set for the integration period, for easy normaliza- tion in the processor ...
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... L.O.s select the upper sideband; positive frequency L.O.s select the lower sideband. The range of the NCO fS/2. The frequency resolution of the NCO is fS/( HSP50214A or approximately 0.015Hz when CLKIN is 65 MSPS and ENI is tied low. The phase of the Carrier NCO can be shifted by adding a 10- bit phase offset to the MSB’ ...
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... Table 1 details the permissible values for the GAINADJ(2:0) barrel shifter control, while Figure 15 shows the permissible CIC Shift Gain values. The CIC filter structure for the HSP50214A is fifth order; that is it has five integrator/comb pairs. A fifth order CIC has 84dB of alias attenuation for output frequencies below 1/8 the CIC output sample rate ...
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... R is the decimation factor and N is the number of stages. The input to the CIC from the mixer is 15 bits, and the bit widths of the accumulators for the five stages in the HSP50214A are 40, 36, 32, 32, and 32, as shown in Figure 16. This limits the maximum decimation in the CIC to 32 for a full scale input ...
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... For example, if only 12 bits are needed, an offset range of 24dB is possible for a decimation of 24. FIGURE 16. CIC FILTER BIT WEIGHTING HSP50214A Since each halfband filter section decimates by 2, the total decimation through the halfband filter is given by: N ...
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... NOTE: While Halfband filters are typically selected starting with the last stage in the filter chain to give the maximum alias free bandwidth, a higher throughput rate may be obtained using other filter combinations. See Application Note 9720, “Calculat- ing Maximum Processing Rates of the PDC”. HSP50214A 0 ALIAS ...
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... For configurations which employ decimation input sample periods may be available for filter calculation. HSP50214A For real filter configurations, use Equation 11 to calculate the number of taps available at a given input filter sample rate. TAPS ...
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... Complex Filters: A filter with quadrature coefficients. FIGURE 20. DEMONSTRATION OF DIFFERENT TYPES OF DIGITAL FIR FILTERS CONFIGURED IN THE PROGRAMMABLE DOWNCONVERTER HSP50214A Automatic Gain Control (AGC) The AGC Section provides gain to small signals, after the large signals and out-of-band noise have been filtered out, to ensure that small signals have suffi ...
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... The AGC loop feedback path consists of an error detector, error scaling, and an AGC loop filter. The error detector sub- tracts the magnitude output of the coordinate converter from HSP50214A the programmable AGC THRESHOLD value. The bit weight- ing of the AGC THRESHOLD value (Control Word 8, Bits 16- 28) is shown in Table 5 ...
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... CONTROL WORD 9 BIT: 27 FORMAT e HSP50214A TABLE 6B. AGC LIMIT MANTISSA vs GAIN MANTISSA GAIN(dB) 511 6.000 0 5.750 0 5.500 0 5.250 0 5.000 0 4.750 0 4.500 0 4.250 0 4.000 0 3.750 0 3.500 0 3.250 0 3.000 0 2.750 0 2 ...
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... AGC gain traces the transfer function given in Figures 21 and 22. Since the log of the gain response is roughly linear, the loop response can be approximated by multiplying the maximum AGC gain error by the loop gain. The expected HSP50214A (RANGE = 0 TO 2.18344 LIMIT ...
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... In the HSP50214, a reset event (caused by SYNCIN2 or CW25) would clear the AGC loop filter accumulator. In the HSP50214A, if Control Word 27, Bit 15 is set to zero, the AGC loop filter accumulator will clear as in the original HSP50214. If Control Word 27, Bit 15 is set to a one, the backend reset (from CW25) will not clear the AGC loop fi ...
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... FREQUENCY (RELATIVE TO f FIGURE 24A. POLYPHASE RESAMPLER FILTER BROADBAND FREQUENCY RESPONSE HSP50214A Optimizing the FIR filter performance provides better use of the programmable FIR taps. Table 10 details the maximum clocking rates for the possible resampling and interpolation halfband filter configurations of this section of the PDC. Con- trol Word 16, Bits 2-0 identify the fi ...
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... Input(Cart/PolarGain)(Error Det Gain)(AGC Loop Gain Max -0 AGC Response = (1)(1.64676)(2 )(1)(0.75dB) ~ 1.23dB/symbol time. Max -15 AGC Response = (1)(1.64676)(2 )(1)(0.75dB) ~ 0.00004dB/symbol time. Min Thus, the expected range for the AGC rate is ~ 0.00004 to 1.23dB/symbol time. HSP50214A AGC LOOP FILTER GAIN MULTIPLIER SHIFT SHIFT (OUTPUT ...
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... NOTES: 1. SRnd = Symmetric Round; Rnd = Round; SAT = Saturation. 2. The NBW out of the CIC filter is 0 SOUT x 16 CIC should (9dB or 1.5 bits) versus A/D noise, the processing gain should be 10log (BW HSP50214A TABLE 9B. PDC BIT WEIGHTING CIC BIT CIC IN WEIGHTS SHIFT = 15 IIIIICCCCC ...
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... CLK necessary to decimate down to 2x the chip rate to get a realistic number of filter taps. Both interpolation halfband filters are then used to obtain the 8x CDMA output. 944 MIPS is a lot of MIPS. The HSP50214A gets the equivalent process- ing by decimating down and interpolating back up. POLYPHASE ...
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... Reference clock. Figure 26 details the block diagram of the timing error generation circuit. The 16 bits of timing error are available both as a PDC serial output and as a processor read parameter. See the Processor Read Section for more details on accessing this value. HSP50214A TIMING FILTER PHASE NCO SELECT ACC ...
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... I and Q. 0.043945312 In the HSP50214A, an additional data path option was added that allows the output of the 255 tap programmable 0.021972656 FIR filter to be routed directly to the coordinate converter. 0.010986328 ...
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... Controlled via microprocessor interface. FIGURE 29. FREQUENCY DISCRIMINATOR BLOCK DIAGRAM The HSP50214A offers an expanded choice of signals to be filtered by the discriminator FIR. The choices are bits of delayed, and subtracted (and optionally shifted) phase. This is the Discriminator FIR filter input found in the HSP50214 ...
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... AOUT bus. The rate at which the data out of the HSP50214 transitions and the rate at which DATARDY is asserted can be different. HSP50214A Data Transitions: The transition rate of the parallel output data is dependent on which of the three types of data is selected for the AOUT Out- put channel: I (real symbols), |r| (magnitude (frequency). Q (quadrature symbols), ø ...
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... sample time + 63 tap FIR impulse response. If the FIR is set to decimate and frequency is selected for AOUT, the DATARDY signal will be at the discriminator FIR output (decimated) rate. FIGURE 33. DATARDY WAVEFORMS WHEN f (FREQUENCY) IS SELECTED AS AOUT HSP50214A Note that the BOUT data word may different rate and skewed in time with respect to DATARDY, depending on the type of data selected for output ...
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... Program these bits into the Control Word 19 field representing the “Link following X data”, where X = the source data type, HSP50214A defines the second word in the sequence. Likewise, the third data word is linked by selecting the Control Word 19 bits that identify the “ ...
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... SERIAL OUTPUT CLOCK POLARITY † SERIAL OUTPUT SYNC POLARITY † Controlled via microprocessor interface ‡ Polarity is programmable FIGURE 34. SERIAL OUTPUT FORMATTER BLOCK DIAGRAM HSP50214A SEROUTB: start |r| data word > f data word > TE data word> AGC data word > end > † † ...
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... SEROUTB. The choices for the remaining data word in the SEROUTB signal are: phase, frequency, AGC level and timing error. Table 15 illustrates how Control Word 19 should be programmed. HSP50214A TABLE 15. EXAMPLE 2 SERIAL OUTPUT CONTROL SETTINGS CONTROL WORD 19 ...
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... SERSYNC PRECEDES MSB “INVERTED” 1 LSB WORD0 MSB WORD1 • • • 2 DATA SHIFT MSB FIRST FIGURE 36. VALID SERSYNC CONFIGURATION OPTIONS HSP50214A DATA WORD 2 DATA WORD 1 Q DATA WORD 2 DATA WORD 1 MAGNITUDE NOTE: Once magnitude is identified to follow ...
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... ADDR – ADDR RAM WRITE READ HSP50214A FIFO Operation via 16-Bit Processor Interface Figure 37 shows the conceptual configuration of the 16-bit Processor interface. This interface looks like a 16-bit Pro- cessor read-only microprocessor interface. The SEL(2:0) lines are the address bus and the OEAL and OEBL lines are the read lines ...
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... Figure 39 shows INTRRP going low before the FIFO is read. The FIFO can be read before the number of samples reaches the INTRRP pointer. The number of samples in the FIFO must be monitored by the user via a status read. HSP50214A INTRRP PDC AOUT(7:0) BOUT(7:0) SEL(2:0) FIGURE 38 ...
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... READY D: FIFO READY IS WHEN (WRITE - READ) > DEPTH FIGURE 40. FIFO REGISTER OPERATION HSP50214A FIFO Operation via 8-Bit Processor Interface The Buffer RAM Output may also be accessed via the 8-bit microprocessor interface C(7:0). Figure 41 shows the con- ceptual configuration of the 8-bit processor interface. Con- trol Word 20, Bit 24 must be set order to obtain Buffer RAM data to this output ...
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... R2, R1, R0 ADDRESS “5” A2, A1 I INPUT AGC 5: AGC; TIMING RD FIGURE 41. 8-BIT MICROPROCESSOR INTERFACE BUFFER RAM MODE BLOCK DIAGRAM PROCCLK I/Q DATARDY (I/Q SELECTED) DATARDY (R/ SELECTED) INTRRPT WRITES TO SNAPSHOT RAM HSP50214A | LSByte STATUS ...
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... Care must be taken to either read sufficient data out of memory or RESET the addressing to ensure that a complete set of data is the cause of the interrupt. HSP50214A INTRRP WR A COMPLETE SET OF 3 DATA SAMPLES IS IN MEMORY AT INTRRP A: NORMAL READ/WRITE SEQUENCE ...
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... REGISTER AND WAIT 4 CLKs FIGURE 45. LOADING THE CONTROL REGISTERS WITH 32-BIT CONTROL WORDS HSP50214A Microprocessor Read Section The microprocessor read uses both read and write proce- dures to obtain data from the PDC. A write must be done to location 5 to select the source of data to be read. The read source is determined by the value placed on the lower three bits of C(7:0) ...
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... Low). (0)-INTEGRATION has been completed in the input level detector and is ready to be read. (Active High). HSP50214A Applications Composite Filter Response Example For this example consider a total receive band roughly 25MHz wide containing 124 200kHz wide FDM channels as shown in Figure 44. The design goal for the PDC is to tune to and fi ...
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... HSP50210 Data Sheet, Intersil Corporation, AnswerFAX Doc. No. 3652. [2] Cellular Radio and Personal Communications: A Book of Selected Readings, Theodore S. Rappaport, 1995 by IEEE, Inc. [3] AN9720 Application Note, Intersil Corporation, “Calcu- lating Maximum Processing Rates of the PDC (HSP50214A)”, AnswerFAX Doc. No. 99720. [4] FO-007 Block Diagram of HSP50214. = 541.667kHz s 44 ...
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... CIC INPUT RATE S -130 FREQUENCY FIGURE 49A. HB5 FILTER RESPONSE 10 -10 -30 -50 -70 -90 -110 -130 FIGURE 49C. COMPOSITE FILTER RESPONSE FIGURE 49. PDC FILTER FREQUENCY SPECTRUMS EXAMPLE (NORMALIZED TO SAME SCALE) HSP50214A 10 -10 -30 -50 -70 -90 -110 f = CIC INPUT RATE S -130 f FREQUENCY S R FIGURE 48B. HB3 FILTER RESPONSE ...
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... Carrier NCO Offset Frequency Enable 0 Carrier NCO Load Phase Accum On Update HSP50214A written to the Master Register. Figure 45 details the timing for proper operation of the Microprocessor Write Section. Bits identified as “Reserved” should be programmed to a zero. DESCRIPTION Reserved. 0- The SYNCIN1 pin has no effect on the Carrier NCO. ...
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... CONTROL WORD 3: CARRIER NCO CENTER FREQUENCY (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION 31-0 Carrier Center Frequency NOTE: In the HSP50214A, if the SYNCIN1 occurs when the NCO is not updating, the load signal is held internal to the part until the next NCO update. CONTROL WORD 4: CARRIER PHASE OFFSET (SYNCHRONIZED TO CLKIN) BIT POSITION FUNCTION 31-10 ...
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... Selected when AGCGNSEL = 0. These bits are MMMM. See description for bits 15-12. Same equations are used for Loop 0. Bit 7 is the MSB. 3-0 Loop Gain 0 Selected when AGCGNSEL = 0. These bits are EEEE. See description for bits 15-12. Same Exponent equations are used for Loop 0. Bit 3 is the MSB. HSP50214A DESCRIPTION DESCRIPTION -(15 - EEEE -10 down to 2 ...
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... These bits control the frequency of the timing NCO. The frequency range of the NCO is from 0 Frequency to F puted by the equation: N =(f register. After loading, a transfer to the Active Register is done by writing to Control Word generating a SYNCIN2 with Control Word 11, Bit 5 set to 1. HSP50214A DESCRIPTION GAIN dB/20 ( ...
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... Resampler and Halfband Filter 1 Enabled. Enabled 100- Not Valid. 101- Not Valid. 110- Both Halfband Filters Enabled. 111- Resampler and Both Halfband Filters Enabled. HSP50214A DESCRIPTION T/2 (2’s complement (offset binary). Bit 7 is DESCRIPTION DESCRIPTION DESCRIPTION puts can be delayed from 2 to 255 clocks from the first output. A delay of 2 equals 255 clocks of delay. A delay invalid mode. When interpolating by 2, one extra output is generated ...
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... The processor then parses out the various data words example, if the I and Q are chained together and a single SERSYNC pulse is generated for this serial output chain, no am- biguity exists in the processor about which two data samples (one from I and one from Q) are related. HSP50214A DESCRIPTION -(ddd + 1) . ...
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... Serial Output at PROCCLK/2. 1XX- Serial Output at PROCCLK rate. 13-12 I Data Serial Output 00- No Tag Bit. LSB of word is passed. Tag Bit 01- 0 Tag Bit. LSB of word is set to zero. 1X- 1 Tag Bit. LSB of word is set to one. HSP50214A DESCRIPTION (SYNCHRONIZED WITH PROCCLK) DESCRIPTION ...
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... SYNCOUT Strobe A write to this address generates a one clock period wide strobe on the SYNCOUT pin that is synchronized to the clock. This strobe may be synchronized to CLKIN or PROCCLK based on the programming of bit 3 of Control Word 0. HSP50214A DESCRIPTION DESCRIPTION 8 ), sample time counts between snapshot samples. Program ...
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... Reloads “Number of Words” counter. 3. Reloads counter for sync (for early or late). 4. Reloads counter for dividing down SERCLK the HSP50214A, the Control Word 25 reset signal is designed such that the front end HSP50214A DESCRIPTION the HSP50214A, a configuration control word bit determines if a Timing NCO reset is ex- ecuted ...
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... A fixed value 0 0010 0111 1010 [027A]hex is loaded here for setting the Sin/Cos Generator out- puts to 7FFF. HSP50214A DESCRIPTION HSP50214A does require that Control Word 25, Bit 24 be set to zero for normal operation, software that was written for the HSP50214 will require modification to work properly with the HSP50214A. DESCRIPTION ...
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... C0_im is the coefficient loaded into CW129. The convolution starts with the oldest data, times the last complex coefficient, and ends with the newest data, times the first complex coefficient loaded. Iout Qout = (Xn-k+1_i * Ck-1_im + Xn-k+1_q * Ck-1_re). HSP50214A DESCRIPTION to C are loaded with C 0 ...
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... C, controlled via design or process parameters and not directly tested. Characterized upon initial design and at A major process or design changes. HSP50214A Thermal Information Thermal Resistance (Typical, Note 4) +0.5V MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... AC tests performed with C = 40pF Test V = 3.0V 4.0V 0V. IH IHC IL 8. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes. 9. Without discriminator/with discriminator. HSP50214A 5 Commercial; - SYMBOL ...
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... AC Test Load Circuit SWITCH S1 OPEN FOR I NOTE: Test head capacitance. Waveforms t WRL WSA WHA t t WSC WHC C(0-7), A(0-2) FIGURE 50. TIMING RELATIVE 2.0V 0.8V FIGURE 52. OUTPUT RISE AND FALL TIMES HSP50214A S DUT 1 C (NOTE AND I CCSB CCOP EQUIVALENT CIRCUIT RD t WRH t AS A(2-0) C(0-7) t RDO FIGURE 51 ...
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... For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 HSP50214A PROCCLK AGCGNSEL, MCSYNC1 SOF, SOFSYNC, SYNCIN2 AOUT(15:0), 1.5V ...