hsp50214a Intersil Corporation, hsp50214a Datasheet - Page 30

• Manufacturer Part Number: hsp50214a
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

The magnitude resolution may suffer because there is no
gain adjustment before computing the magnitude. If the sig-
nal is < - 90dBFS, it will be below the LSB of the magnitude
output.
The enable signal for gating data into the coordinate con-
verter is either the AGC data ready signal or the resampler
data ready signal. If the resampler is bypassed, the AGC
data ready signal is used and there is a delay of 6 clock
cycles between the FIR data being ready and the coordinate
converter block sampling it. If the resampler is enabled, its
data ready signal will be delayed by 6 clocks (for the AGC)
plus the compute delay of the resampler block. This may
cause the I/Q to |r|/ output sample alignment to shift with
decimation. For this reason, it is recommended that the res-
ampler/halfband filter block be bypassed when using this
new data path.
To select the output of the 255 tap programmable FIR filter to
be routed to the coordinate converter, set Control Word 27,
Bit 13 to a logic one. For routing as in the HSP50214, set
Control Word 27, Bit 13 to a logic zero.
Frequency Discriminator
The discriminator block delays phase from the Cartesian to
Polar Section and subtracts it from the latest sample. This
delay and subtract can be modeled as a programmable
delay comb filter. The output of the filter is d /dt, or fre-
quency. The transfer function of the discriminator is set by
where D is the programmable discriminator delay expressed
in number of sample clock delays. The discriminator output
frequency is then filtered with a programmable FIR filter. The
Block Diagram of the Frequency Discriminator is shown in
Figure 29.
The range of delay in the discriminator is from 1 to 8 sam-
ples. Modulo 2 subtraction eliminates rollover problems in
the subtraction at 2 . The alias free discriminator frequency
range is given by:
Range
where D is the discriminator delay defined in Equation 21
(1 < D < 8), F
sample rate and CW is the desired center frequency. When
the phase multiplier is set to a value other than 2
criminator range is reduced proportionally. The phase multi-
plier can be 1, 2, 4 or 8 (2
reduces the range by 2, a multiply of 2
by 4, and a multiply of 2
The FIR filter can be configured with up to 63 symmetric taps
and up to 32 asymmetric taps. In the symmetric mode, the
FIR can be configured for even or odd symmetry, as well as
with an even or odd number of filter taps. Decimation is pro-
vided to allow more processing time for longer (i.e., more
taps) filter structures.
H z
=
FREQDISC
1 Z
–
–
D
SAMPOUT
=
CW
3
is the Discriminator FIR filter output
F
reduces the range by 8.
SAMPOUT
0
to 2
3
). Thus, a multiply of 2
D
+
2
1
reduces the range
;
0
, the dis-
(EQ. 21)
(EQ. 22)
HSP50214A
1
30
†
The HSP50214A offers an expanded choice of signals to be
filtered by the discriminator FIR. The choices are:
1) 18 bits of delayed, and subtracted (and optionally shifted)
phase. This is the Discriminator FIR filter input found in the
HSP50214.
2) 18 bits of magnitude from the coordinate converter block.
This was added to provide for post-detection filtering of AM
signals.
3) 18 bits from the I output of the resampler/interpolation
halfband filter block. This was added to provide for process-
ing of SSB signals.
The shift, delay, and subtract functions are bypassed for
items (2) and (3).
In addition to the FIR input selections, the Q input to the
coordinate converter block can be zeroed so that the magni-
tude output is the magnitude of I only. Again this was added
to provide for processing SSB signals.
The Discriminator FIR filter input selections are made in
Control Word 27, Bits 18 and 19. The bit definitions are:
Control Word 27, Bit 14 is used to control the Q input to the
coordinate converter. The bit definitions is:
The enable signals associated with the various input selec-
tions to the Discriminator FIR filter are:
FIGURE 29. FREQUENCY DISCRIMINATOR BLOCK DIAGRAM
Controlled via microprocessor interface.
DISCRIMINATOR DELAY
00
01
1X
0
1
1
2
DISC. FIR DECIMATION
FIR SYMMETRY TYPE
PHASE MULTIPLIER
DISCRIMINATOR EN
FIR COEFFICIENTS
I and Q enabled to the I/Q to R/Theta block.
The Q input to the I/Q to R/Theta block is zeroed.
The data ready strobe from the coordinate con-
verter block.
The data ready strobe from the coordinate con-
verter block.
PHASE INPUT
FIR SYMMETRY
Item (1) described above.
Item (2) described above.
Item (3) described above.
FIR TAPS
†
†
†
†
†
†
†
†
63-TAP
FILTER
DELAY
-
(1-8)
FIR
+
+
FREQ(15:0)