hsp50214a Intersil Corporation, hsp50214a Datasheet - Page 42

• Manufacturer Part Number: hsp50214a
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

Suppose a (0018D038)H needs to be loaded into Control Word
0, then Table 20 details the steps to be taken.
(PROCCLK,
FIGURE 45. LOADING THE CONTROL REGISTERS WITH
A2-0
C7-0
A2-0
STEP
WR
0
1
2
3
4
5
TABLE 20. EXAMPLE PROCESSOR WRITE SEQUENCE
1
2
3
4
5
6
CLKIN)
CLK =
Holding Register 0. Transfers to bits 7-0 of the 32-bit Des-
tination Register. Bit 0 is the LSB of the 32-bit register.
Holding Register 1. Transfers to bits 15-8 of a 32-bit Desti-
nation Register.
Holding Register 2. Transfers to bits 23-16 of a 32-bit Des-
tination Register.
Holding Register 3. Transfers to bits 31-24 of a 32-bit Des-
tination Register. Bit 31 is the MSB of the 32-bit register.
This is the Destination Address Register. On the fourth
CLK following a write to this register, the contents of the
Holding Registers are transferred to the Destination Reg-
ister. All 8 bits written to this register are decoded into the
Destination Register Address. The configuration destina-
tion address map is given in the tables in the Control Word
Section.
Selects data source for reading. See Microprocessor Read
Section.
LSB
TABLE 19. DEFINITION OF ADDRESS MAP
CONFIGURATION
0
A(2:0)
000
001
010
011
100
32-BIT CONTROL WORDS
1
LOAD
DATA
2
0011 1000
1101 0000
0001 1000
0000 0000
0000 0000
C(7:0)
REGISTER DESCRIPTION
MSB ADD
3
4
LOAD ADDRESS OF
TARGET CONTROL
Loads 38 into Master Register
(7:0) on rising edge of WR.
Loads D0 into Master Register
(15:8) on rising edge of WR.
Loads 18 into Master Register
(23:16) on rising edge of WR.
Loads 00 into Master Register
(31:24) on rising edge of WR.
Load “0018D038” into Configu-
ration Control Register 0.
Wait 4 CLKS.
REGISTER AND
WAIT 4 CLKs
1
2
COMMENT
3
4
LOAD NEXT
REGISTER
0
URATION
CONFIG-
HSP50214A
2
42
Microprocessor Read Section
The microprocessor read uses both read and write proce-
dures to obtain data from the PDC. A write must be done to
location 5 to select the source of data to be read. The read
source is determined by the value placed on the lower three
bits of C(7:0). The output from a particular read code is
selected using a read address placed on A(2:0). The output
is sent to C(7:0) on the falling edge of RD.
If the Read Address is equal to 111, the Read Code is
ignored, and the status bits shown in Table 22 in the Output
Section is sent to C(7:0). This state was provided so that the
user could obtain the status bits quickly.
Refer to the Timing Diagram in Figure 43. Suppose the input
level detector has a hex value of (321AF5)H, then Table 21
details the steps to be taken.
TABLE 21. PROCESSOR READ SEQUENCE (INPUT LEVEL
PROCLK
FIGURE 46. READING THE CONTROL REGISTERS USING A
STEP
CONTROL REGISTER
A2-0
C7-0
1
2
3
4
WR
LOAD ADDRESS
RD
OF TARGET
SELECTOR)
A(2:0)
READ CODE C(2:0)
LATCH CODE EQUAL TO A 5, A READ ADDRESS
AND A READ CODE
101
000
001
010
5
1111 1000
0001 1010
0011 0010
THREE-STATE
INPUT BUS
C(7:0)
(F4)H
(1A)H
(32)H
100
READ ADDRESS
Write Read Code, 100 to
Address 5, WR pulled high to
generate rising edge.
Drop RD low, Read AGC
LSB.
Pull RD high, then drop low,
Read AGC NLSB.
Pull RD high, then drop low,
Read AGC MSB.
TO ENABLE DATA
OUTPUT ON C0-7
OUTPUT DATA C(7:0)
ASSERT RD
COMMENT