hsp50214a Intersil Corporation, hsp50214a Datasheet - Page 14

• Manufacturer Part Number: hsp50214a
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

The carrier offset frequency is loaded using the COF and
COFSYNC pins. Figure 13 details the timing relationship
between COF, COFSYNC and CLKIN. The offset frequency
word can be zeroed if it is not needed. Similarly, the
Sample Offset Frequency Register controlling the Re-
Sampler NCO is loaded via the SOF and SOFSYNC pins.
The procedure for loading data through the two pin NCO
interfaces is identical except that the timing of SOF and
SOFSYNC is relative to PROCCLK.
Each serial word has a programmable word width of either 8,
16, 24, or 32 bits (See Control Word 0, Bits 4 and 5, for the
Carrier NCO programming and Control Word 11, Bits 3 and
4, for Timing NCO programming). On the rising edge of the
clock, data on COF or SOF is clocked into an input shift reg-
ister. The beginning of a serial word is designated by assert-
ing either COFSYNC or SOFSYNC “high” one CLK period
prior to the first data bit.
NOTE: Serial Data must be loaded MSB first, and COFSYNC or
NOTE: COF loading and timing is relative to CLKIN while SOF
NOTE: T
FIGURE 14. HOLDING REGISTERS LOAD SEQUENCE FOR
†
†
IGURE 13. SERIAL INPUT TIMING FOR COF AND SOF INPUTS
OTE: Data must be loaded MSB first.
COFSYNC/
32
SOFSYNC
24
16
Serial word width can be: 8, 16, 24, 32 bits wide.
T
8
30
28
26
22
20
18
14
12
10
D
†
†
†
†
6
4
2
0
CLKIN
is determined by the COFSYNC, COFSYNC rate.
COF/
SOF
SOFSYNC should not be asserted for more than one CLK
cycle.
loading and timing is relative to PROCCLK.
D
2
can be 0, and the fastest rate is with 8-bit word width.
6
COF AND SOF SERIAL OFFSET FREQUENCY
DATA
10
14
CLK TIMES
MSB
18
COFSYNC, SOFSYNC
(8)
TO HOLDING REGISTER
ASSERTION OF
22
(16)
DATA TRANSFERRED
26
(24)
30
(32)
34
LSB
T
T
T
T
38
D
D
D
D
††
††
††
††
MSB
42
46
50
HSP50214A
54
14
The assertion of the COFSYNC (or SOFSYNC) starts a count
down from the programmed word width. On following CLKs,
data is shifted into the register until the specified number of
bits have been input. At this point the contents of the register
are transferred from the Shift Register to the respective 32-bit
Holding Register. The Shift Register can accept new data on
the following CLK. If the serial input word is defined to be less
than 32 bits, it will be transferred to the MSBs of the 32-bit
Holding Register and the LSBs of the Holding Register will be
zeroed. See Figure 14 for details.
CIC Decimation Filter
The mixer output may be filtered with the CIC filter or it may be
routed directly to the halfband filters. The CIC filter is used to
reduce the sample rate of a wideband signal to a rate that the
halfbands and programmable filters can process, given the
maximum computation speed of PROCCLK. (See Halfband
and FIR Filter Sections for techniques to calculate this value).
Prior to the CIC filter, the output of the mixer goes through a
barrel shifter. The shifter is used to adjust the gain in 6dB
steps to compensate for the variation in CIC filter gain with
decimation. (See Equation 6). Fine gain adjustments must
be done in the AGC Section. The shifter is controlled by the
sum of a 4-bit CIC Shift Gain word from the microprocessor
and a 3-bit gain word from the GAINADJ(2:0) pins. The three
bit value is pipelined to match the delay of the input samples.
The sum of the 3 and 4-bit shift gain words saturates at a
value of 15. Table 1 details the permissible values for the
GAINADJ(2:0) barrel shifter control, while Figure 15 shows
the permissible CIC Shift Gain values.
The CIC filter structure for the HSP50214A is fifth order; that
is it has five integrator/comb pairs. A fifth order CIC has
84dB of alias attenuation for output frequencies below 1/8
the CIC output sample rate.
The decimation factor of the CIC filter is programmed in Con-
trol Word 0, Bits 12 - 7. The CIC Shift Gain is programmed in
Control Word 0, Bits 16-13. The CIC Bypass is set in Control
Word 0, Bit 6. When bypassing the CIC filter, the ENI signal
must be deasserted between samples, i.e., the C
must be
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
4
8
2 f
12
FIGURE 15. CIC SHIFT GAIN VALUES
S
.
16
20
8-BIT INPUT
10-BIT INPUT
12-BIT INPUT
14-BIT INPUT
24
28
DECIMATION (R)
32
36
ALLOWABLE CIC SHIFT
GAINS ARE BELOW THE
CURVES
40
44
48
52
LKIN
56
60
note
64