hsp50214a Intersil Corporation, hsp50214a Datasheet - Page 47

• Manufacturer Part Number: hsp50214a
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

NOTE: In the HSP50214A, if the SYNCIN1 occurs when the NCO is not updating, the load signal is held internal to the part until the next
NCO update.
POSITION
POSITION
POSITION
POSITION
POSITION
POSITION
29-14
31-10
13-0
31-0
N/A
N/A
N/A
BIT
BIT
BIT
BIT
BIT
BIT
9-0
31
30
Reserved
Integration Mode
Integration Interval
Input Threshold
Start Input Level
Detector AGC
Integrator
Carrier Center
Frequency
Reserved
Carrier Phase Offset
Carrier Frequency
Strobe
Carrier Phase Strobe
CONTROL WORD 2: INPUT LEVEL DETECTOR START STROBE (SYNCHRONIZED TO CLKIN)
CONTROL WORD 3: CARRIER NCO CENTER FREQUENCY (SYNCHRONIZED TO CLKIN)
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
CONTROL WORD 5: CARRIER FREQUENCY STROBE (SYNCHRONIZED TO CLKIN)
CONTROL WORD 6: CARRIER PHASE STROBE (SYNCHRONIZED TO CLKIN)
CONTROL WORD 4: CARRIER PHASE OFFSET (SYNCHRONIZED TO CLKIN)
CONTROL WORD 1: INPUT LEVEL DETECTOR (SYNCHRONOUS TO CLKIN)
Reserved.
0- Integration of magnitude error stops when the interval counter times out.
1- Integration runs continuously. When the interval counter times out, the integrator reloads, and
the results of the integration is sent to a register for the processor to read.
These are the top 16 bits of the 18-bit integration counter, ICPrel. ICPrel = (N)/4+1; where N is
the desired integration period in CLKIN cycles, defined as the number of input samples to be
integrated. N must be a multiple of 4: [0, 4, 8, 12, 16 .... , 2
interpolated, then the zeros must be accounted for, as they will be added to the threshold! If the
gated input mode is used, the same input sample will be accumulated multiple times.
Input Magnitude Threshold. Bits 12-0 correspond to input bits 12-0. The magnitude of the input
is added to this threshold, where the threshold is a signed number. Bit 13 is the MSB.
Writing to this location starts/restarts the input AGC error integrator. The integrator will either
restart or stop when the integration interval counter times out depending on bit 30 of Control
Register 1 (see Microprocessor Write Section).
These bits control the frequency of the Carrier NCO. The frequency range of the NCO is F
where f
Bit 31 is the MSB. This location is a holding register. After loading, a transfer to the active reg-
ister is done by writing to Control Word 5 or by generating a SYNCIN1 with Control Word 0, Bit
20 set to 1. The Carrier NCO only updates when ENI is active.
Reserved.
These bits, PO, are used to offset the phase of the carrier NCO. The bits are computed by the
Equation PO = INT[(2
from 0 to 2 for 10-bit offset binary representation. Bit 9 is the MSB. This location is a holding
register. After loading, a transfer to the active register is done by writing to Control Word 6 or by
generating a SYNCIN1 with Control Word 0, Bit 20 set to 1.
Writing to this address updates the carrier frequency Control Word from the Holding Register.
Writing to this address updates the carrier phase offset Control Word with the value written to
the phase offset (PO) register.
S
is the input sample rate. The bits are computed by the equation N = (F
HSP50214A
10
47
off
)/ 2 ]
HEX
; (- <
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
off
< ) for 10-bit 2’s complement representation or
18
]. Bit 29 is the MSB. If the input is
NCO
/ F
S
)*2
S
32
/2
.