hsp50214a Intersil Corporation, hsp50214a Datasheet - Page 37

• Manufacturer Part Number: hsp50214a
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

Buffer RAM Output Port
The Buffer RAM parallel output mode utilizes a RAM to store
output data for future retrieval by either the 8-bit microproces-
sor that is configuring the PDC or by a 16-bit baseband pro-
cessing engine (which could also be a microprocessor). Data
is output from the RAM only on request and can be obtained
from either the 8-bit P interface or from a 16-bit interface that
uses the two LSBytes of AOUT and BOUT. The RAM holds up
to eight 80-bit sample sets. Each sample set includes 16 bits
of each I, Q, magnitude, phase, and frequency data. The
RAM samples are mapped as shown in Table 16. The Buffer
RAM controller supports both FIFO and Snapshot modes.
NOTE: I and Q are sample aligned in time. |r| and
The FIFO mode allows the processor to service the interface
only when enough samples are present in the RAM. This
mode is provided so that the Processor does not have to
service the PDC every output sample. An interrupt,
INTRRPT, is asserted when the desired number of samples
are available. The PDC can be programmed to assert the
interrupt when up to 7 samples are available. Control Word
21, Bit 15 is used to set the Buffer RAM controller to the
FIFO mode, while Control Word 21, Bits 12-14 set the num-
ber of RAM samples to be stored (0 to 7) before the interrupt
(INTRRPT) is asserted. Control Word 20, Bit 24 determines
whether the RAM output interface is the 8-bit microprocessor
interface or the 16-bit processor interface. In the 16-bit inter-
face the MSByte is sent to AOUT(7:0) while the LSByte is
sent to BOUT(7:0).
The INTRRP output signal goes low for 8 PROCCLK cycles
when the number of samples in the Buffer RAM (depth)
reaches the programmed depth. The depth of the RAM is
calculated using Equation 23. A DSP microprocessor or the
data processing engine can use the INTRRP signal to know
that the RAM is ready to be read.
D
SAMPLE
RAM
RAM
SET
0
1
2
3
4
5
6
7
aligned in time, but one sample delayed from I or Q. The
frequency sample is delayed in time from I or Q by 1
sample time + 63 tap FIR impulse response. If the FIR is
set to decimate, the FIR output will be repeated every
sample time until a new value appears at the filter output.
(i.e., the frequency samples are clocked out at the I, Q
sample rate regardless of decimation.)
=
ADDR
I
I
I
I
I
I
I
I
TABLE 16. RAM DATA STORAGE MAP
DATA
0
1
2
3
4
5
6
7
(000)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
I
WRITE
Q
Q
Q
Q
Q
Q
Q
Q
DATA
(001)
0
1
2
3
4
5
6
7
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
–
Q
ADDR
|r|
|r|
|r|
|r|
|r|
|r|
|r|
|r|
READ
DATA
(010)
0
1
2
3
4
5
6
7
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
|r|
–
1
MOD8
DATA
0
1
2
3
4
5
6
7
(011)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
are sample
f
f
f
f
f
f
f
f
0
1
2
3
4
5
6
7
DATA
(EQ. 23)
(100)
HSP50214A
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
(15:0)
F
37
FIFO Operation via 16-Bit Processor
Interface
Figure 37 shows the conceptual configuration of the 16-bit
cessor read-only microprocessor interface. The SEL(2:0)
lines are the address bus and the OEAL and OEBL lines are
the read lines. The address is decoded as shown in
Table 17.
Use of the 16-bit interface for Buffer RAM output requires
Control Word 20, Bit 25, to be set to a logic “0” and Control
Word 20, Bit 24, to be set to a logic “1”. Once the Control
Word 20 has been set to route data to AOUT(7:0) and
BOUT(7:0), then the microprocessor must place a value on
the PDC input pins SEL(2:0), to choose which data type will
be output on AOUT(7:0) and BOUT(7:0). Table 17 defines
the data types in terms of SEL(2:0). With the control lines
set, the selected data is read MSByte on AOUT(7:0) and
LSByte on BOUT(7:0) when OEAL and OEBL (are low).
New data only read when OEBL goes low, so use P for 8-
bit modes. Programming SEL(2:0) = 110 outputs a 16-bit
status signal on AOUT and BOUT. The FIFO status includes
FULL, EMPTY, FIFO Depth, and READYB. These status sig-
nals are defined in Table 18.
|r|
Q
DATA
FIGURE 37. 16-BIT MICROPROCESSOR INTERFACE
NEW
Processor interface. This interface looks like a 16-bit Pro-
I
SEQUENCER
TABLE 17. BUFFER RAM OUTPUT SELECT DEFINITIONS
WRITE
16
16
16
16
16
SEL(2:0)
000
001
010
011
100
101
110
111
BUFFER RAM MODE BLOCK DIAGRAM
“SET OF WORDS”
INCR
WR
SEQUENCER
PROCCLK
ADDRESS
DUAL
PORT
RAM
I Data
Q Data
Magnitude
Phase
Frequency
Unused
Memory Status
Reading this address increments to the next
sample set
INCR
RD
OUTPUT DATA TYPE
I
Q
|r|
STATUS
0
1
2
3
4
6
OUTPUT
DATA
OEBL
SEL(2:0)