hsp50214a Intersil Corporation, hsp50214a Datasheet - Page 13

• Manufacturer Part Number: hsp50214a
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

The frequency of the NCO is the sum of a center frequency
Control Word, loaded via the microprocessor interface (Con-
trol Word 3, Bits 0 to 31), and an offset frequency, loaded seri-
ally via the COF and COFSYNC pins. The offset frequency
can be zeroed in Control Word 0, Bit 1. Both frequency control
terms are 32 bits and the addition is modulo 232. The output
frequency of the NCO is computed as:
or in terms of the programmed value:
where N is the 32-bit sum of the center and offset frequency
terms, fC is the frequency of the carrier NCO sinusoids, f
the input sampling frequency, and INT is the integer of the
computation. See the Microprocessor Write Section on
instructions for writing Control Word
†
For example, if N is 3267 (decimal), and f
is 49.44Hz. If received data is modulated at a carrier fre-
quency of 10MHz, then the synthesizer/mixer should be pro-
grammed for N = 27627627 (hex) or D89D89B9 (hex).
Because the input enable, ENI, controls the operation of the
phase accumulator, the NCO output frequency is computed
relative to the input sample rate, f
quency control, N, is interpreted as two’s complement
because the output of the NCO is quadrature. Negative fre-
quency L.O.s select the upper sideband; positive frequency
L.O.s select the lower sideband. The range of the NCO is -
fS/2 to + fS/2. The frequency resolution of the NCO is fS/(2 32 )
ENABLE
COFSYNC
f
N
SYNCIN1
C
Controlled via microprocessor interface.
=
=
COF
COF
INT f
f
ENI
S
FIGURE 12. BLOCK DIAGRAM OF NCO SECTION
* N
†
C
COF
ACCUMULATOR
CIRCUITRY
2
SYNC
SHIFT REG
32
2
32
SYNC
32
PHASE
MUX
REG
,
f
S HEX
0
COS
TO MIXERS
18
SIN/COS
18
,
32
ROM
REG
REG
REG
REG
REG
+
+
18
CF
FREQUENCY
SIN
10
CARRIER
R
G
E
S
MUX
f
C
3.
, not to f
FREQUENCY
STROBE
CARRIER
STROBE
CARRIER
G
R
E
PHASE
0
†
S
is 65MHz, then fC
G
R
E
†
CLKIN
†
CARRIER
PHASE
OFFSET
. The fre-
ACCUM
CLEAR
PHASE
UPDATE
†
CARRIER
LOAD ON
(EQ. 3A)
HSP50214A
(EQ. 3)
S
†
is
†
13
or approximately 0.015Hz when CLKIN is 65 MSPS and ENI
is tied low.
The phase of the Carrier NCO can be shifted by adding a 10-
bit phase offset to the MSB’s (modulo 360o) of the output of
the phase accumulator. This phase offset control has a reso-
lution of 0.35o and can be interpreted as two’s complement
from -180o to 180o (-p to p) or as binary from 0 to 360o (0 to
2p). The phase offset is given by:
or, in terms of the parameter to be programmed:
where PO is the 10-bit two’s complement value loaded into the
Phase Offset Register (Control Word 4, Bits 9-0). For example,
a value of 32 (decimal) loaded into the Phase Offset Register
would produce a phase offset of 11.25o and a value of -512
would produce an offset of 180o. The phase offset is loaded via
the microprocessor interface. See the Microprocessor Write
Section on instructions for writing Control Word 4.
The most significant 18 bits from the phase adder are used as
the address a sin/cos lookup table. This lookup table maps
phase into sinusoidal amplitude. The sine and cosine values
have 18 bits of amplitude resolution. The spurious compo-
nents in the sine/cosine generation are at least -98dBc. The
sine and cosine samples are routed to the mixer section
where they are multiplied with the input samples to translate
the signal of interest to baseband.
The mixer multiplies the 14-bit input by the 18-bit quadrature
sinusoids. The mixer equations are:
The mixer output is rounded symmetrically to 15 bits.
To allow the frequency and phase of multiple parts to be
updated synchronously, two sets of registers are used for
latching the center frequency and phase offset words. The off-
set phase and center frequency Control Words are first
loaded into holding registers. The contents of the holding reg-
isters are transferred to active registers in one of two ways.
The first technique involves writing to a specific Control Word
Address. A processor write to Control Word 5, transfers the
center frequency value to the active register while a processor
write to Control Word 6 transfers the phase offset value to the
active register.
The second technique, designed for synchronizing updates to
multiple parts, uses the SYNCIN1 pin to update the active
registers. When Control Word 1, Bit 20 is set to 1, the
SYNCIN1 pin causes both the center frequency and Phase
Offset Holding Registers to be transferred to active registers.
Additionally, when Control Word 0, Bit 0 is set to 1, the feed-
back in the phase accumulator is zeroed when the transfer
from the holding to active register occurs. This feature pro-
vides synchronization of the phase accumulator starting
phase of multiple parts. It can also be used to reset the phase
of the NCO synchronous with a specific event.
PO
I
Q
OUT
OFF
OUT
=
=
=
INT 2
=
I
2
IN
I
IN
cos
10
PO 2
sin
OFF
c
c
10
;
2
–
2
HEX
9
–
1
;
–
PO
OFF
2
9
–
1
(EQ. 4A)
(EQ. 5A)
(EQ. 4)
(EQ. 5)