hsp50214a Intersil Corporation, hsp50214a Datasheet - Page 29

• Manufacturer Part Number: hsp50214a
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

Cartesian to Polar Converter
The Cartesian to Polar converter computes the magnitude
and phase of the I/Q vector. The I and Q inputs are 18 bits.
The converter phase output is 16 bits (truncated) with the 16
MSB’s routed to the output formatter and all 18 bits routed to
the frequency discriminator. The 16-bit output phase can be
interpreted either as two’s complement (-0.5 to approxi-
mately 0.5) or unsigned (0.0 to approximately 1.0), as shown
in Figure 28. The phase conversion gain is 1/2 . The phase
resolution is 16 bits. The 16-bit magnitude is unsigned binary
format with a range from 0 to 2.32. The magnitude conver-
sion gain is 1.64676. The magnitude resolution is 16 bits.
The MSB is always zero.
Table 11 details the phase and magnitude weighting for the
16 bits output from the PDC.
The magnitude and phase computation requires 17 clocks
for full precision. At the end of the 17 clocks, the magnitude
and phase are latched into a register to be held for the next
stage, either the output formatter or frequency discriminator.
If a new input sample arrives before the end of the 17 cycles,
the results of the computations up until that time, are
FIGURE 28. PHASE BIT MAPPING OF COORDINATE
8000
7fff
15 (MSB)
0 (LSB)
BIT
14
13
12
11
10
9
8
7
6
5
4
3
2
1
4000
TABLE 11. MAG/PHASE BIT WEIGHTING
bfff
CONVERTER OUTPUT
+
-
/2
Q
/2
c000
3ff f
I
0000
ffff
0
MAGNITUDE
2
2
(Always 0)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
-10
-11
-12
-13
-1
-2
-3
-4
-5
-6
-7
-8
-9
1
0
8000
7fff
4000
180
90
45
22.5
11.25
5.625
2.8125
1.40625
0.703125
0.3515625
0.17578125
0.087890625
0.043945312
0.021972656
0.010986328
0.005483164
bfff
3 /2
/2
PHASE (
Q
c000
3fff
I
0000
ffff
HSP50214A
o
0
)
29
latched. This latching means that an increase in speed
causes only a decrease in resolution. Table 12 details the
exact resolution that can be obtained with a fixed number of
clock cycles up to the required 17. The input magnitude and
phase errors induced by normal SNR values will almost
always be worse than the Cartesian to Polar conversion.
In the HSP50214, the input to the coordinate converter I/Q to
|r|/
is not used, the quantization noise can become a contribut-
ing factor in the phase and frequency computations. For
example, if the signal range is 84dB and the maximum signal
is set at full scale, the minimum signal would have only 4 bits
each for I and Q.
In the HSP50214A, an additional data path option was
added that allows the output of the 255 tap programmable
FIR filter to be routed directly to the coordinate converter.
Rather than having to select only 18 bits out of the available
26 bit output, all 26 bits of the FIR output are routed to the
coordinate converter. This change eliminates quantization
effects to give more accuracy in the phase and frequency
discriminator outputs. The AGC settling time is not a factor
because the AGC is effectively bypassed for the magnitude,
phase, and frequency computations.
NOTE: The most significant 18 bits of the computed phase are
One caveat to selecting the FIR outputs to be routed directly
to the coordinate converter is that because the I/Q samples
for the coordinate conversion are chosen from before the
resampler, the magnitude and phase samples will not align
with the I/Q samples, if the resampler or interpolation half-
band filters are used.
This optional signal routing mode was intended for FM or for
burst PSK where a fixed decimation can be used. It is also
applicable when resampling or timing adjustments on the
demodulated samples are done in a processor following
PDC.
†
Assumes 180
TABLE 12. MAG/PHASE ACCURACY vs CLOCK CYCLES
CLOCKS
block is 18 bits. If the signal range is large and the AGC
10
11
12
13
14
15
16
17
still routed to the discriminator.
6
7
8
9
o
MAGNITUDE
= FS.
ERROR
(% F
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
<0.004
0.065
0.016
0.004
S
)
(DEG.)
ERROR
0.00175
PHASE
0.0035
0.056
0.028
0.014
0.007
0.45
0.22
0.11
3.5
1.8
0.9
†
ERROR
PHASE
(% FS)
0.062
0.016
0.008
0.004
0.002
0.001
0.25
0.12
0.03
0.5
2
1