tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 54

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.4 Reset Control Circuit
2. CPU Core
RA001
2.4.3 Functions
Note 1: IRSTSR is initialized by an external reset input or power-on reset.
Note 2: Care must be taken in system designing since the IRSTSR may not fulfill its functions due to disturbing noise and other
Note 3: IRSTSR<FCLR> is initialized by a power-on reset, an external reset input or an internal reset factor.
Note 4: Set IRSTSR<FCLR> to "1" and write 0x71 to SYSCR4. This enables IRSTSR<FCLR> and the internal factor reset detec-
Note 5: After IRSTSR<FCLR> is modified, SYSCR4 should be written 0x71 (Enable code for IRSTSR<FCLR> in NORMAL mode
Note 6: Bit 7 of IRSTSR is read as "0".
the clock generator.
warm-up operation that follows reset release.
exclusive use memory for adjustment of the ladder resistor that generates the comparison voltage for the
power-on reset and the voltage detection circuits.
from the reset vector address stored in addresses 0xFFFE to 0xFFFF.
circuit is reset.
for the initialization of some special function registers and the initialization of the voltage detection circuits.
The power-on reset, external reset input and internal factor reset signals are input to the warm-up circuit of
During reset, the warm-up counter circuit is reset, and the CPU and the peripheral circuits are reset.
After reset is released, the warm-up counter starts counting the high frequency clock (fc), and executes the
During the warm-up operation that follows reset release, the trimming data is loaded from the non-volatile
When the warm-up operation that follows reset release is finished, the CPU starts execution of the program
When a reset signal is input during the warm-up operation that follows reset release, the warm-up counter
The reset operation is common to the power-on reset, external reset input and internal factor resets, except
When a reset is applied, the peripheral circuits become the states as shown in Table 2-5.
effects.
tion status register is clear to "0". IRSTSR<FCLR> is cleared to "0" automatically after initializing the internal factor reset
detection status register.
when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, IRSTSR<FCLR> may be enabled at unexpected timing.
LVD2RF
LVD1RF
TRMDS
TRMRF
WDTRF
SYSRF
FLSRF
FCLR
Flag initialization control
Flash standby reset detection flag
Trimming data status
Voltage detection reset 2 detection flag
Voltage detection reset 1 detection flag
System clock reset detection flag
Watchdog timer reset detection flag
Trimming data reset detection flag
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0 :-
1 : Clears the internal factor reset flag to "0".
0 :-
1 : Detects the flash standby reset.
0 :-
1 : Detect state of abnormal trimming data
0 :-
1 : Detects the trimming data reset.
0 :-
1 : Detects the voltage detection 2 reset.
0 :-
1 : Detects the voltage detection 1 reset.
0 :-
1 : Detects the system clock reset.
0 :-
1 : Detects the watchdog timer reset.
TMP89FM42