tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 31

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA001
Warm-up counter data register
Clock gear control register
2.3.3 Functions
(0x0FCE)
(0x0FCF)
WUCDR
CGCR
2.3.3.1
Note 1: Don't start the warm-up counter operation with WUCDR set at "0x00".
Note 1: fcgck: Gear clock [Hz], fc: High-frequency clock [Hz]
Note 2: Don't change CGCR<FCGCKSEL> in the SLOW mode.
Note 3: Bits 7 to 2 of CGCR are read as "0".
FCGCKSEL
WUCDR
Read/Write
Read/Write
Bit Symbol
Bit Symbol
peripheral circuits.
clock.
chapter of I/O Ports.
P0FC0 to "1" and then set SYSCR2<XEN> to "1".
set P0FC2 to "1" and then set SYSCR2<XTEN> to "1".
oscillator between the XIN and XOUT pins and between the XTIN and XTOUT pins respectively.
XIN/XTIN pins and the XOUT/XTOUT pins are kept open.
clock oscillation circuit and switching the pin function to ports are controlled by the software and hard-
ware.
trol register P0FC.
After reset
After reset
Clock generator
The clock generator generates the basic clock for the system clocks to be supplied to the CPU core and
It contains two oscillation circuits: one for the high-frequency clock and the other for the low-frequency
The oscillation circuit pins are also used as ports P0. For the setting to use them as ports, refer to the
To use ports P00 and P01 as the high-frequency clock oscillation circuits (the XIN and XOUT pins), set
To use ports P02 and P03 as the low-frequency clock oscillation circuits (the XTIN and XTOUT pins),
The high-frequency (fc) clock and the low-frequency (fs) clock can easily be obtained by connecting an
Clock input from an external oscillator is also possible. In this case, external clocks are applied to the
Enabling/disabling the oscillation of the high-frequency clock oscillation circuit and the low-frequency
The software control is executed by SYSCR2<XEN>, SYSCR2<XTEN> and the P0 port function con-
Clock gear setting
R
7
0
7
0
-
R
6
1
6
0
-
R
5
1
5
0
00 :
01 :
10 :
-
11 :
Page 17
fcgck = fc / 4
fcgck = fc / 2
fcgck = fc
Reserved
Warm-up time setting
R
4
0
4
0
-
WUCDR
R/W
R
3
0
3
0
-
R
2
1
2
0
-
1
1
1
0
FCGCKSEL
R/W
TMP89FM42
0
0
0
0