tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 203

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA002
(Example)
regardless of the T00MOD<DBE1> setting.
When a read instruction is executed on T01+00REG, the last value written into T01+00REG is read out,
Operate TC00 and TC01 in the 16-bit timer mode with the operation clock of fcgck/2 [Hz] and generate interrupts at 96 Ps
intervals (fcgck = 10 MHz)
LD
DI
SET
EI
LD
LD
LD
LD
executed using a new set value after the up counter overflows. Therefore, the interrupt request
interval may be longer than the selected time. If the value set to T01+00REG is equal to the up
counter value, the match detection is executed immediately after data is written into
T01+00REG. Therefore, the interrupt request interval may not be an integral multiple of the
source clock. If these are problems, enable the double buffer.
is stopped, the set value is immediately stored in T01+00REG.
If the value set to T01+00REG is smaller than the up counter value, the match detection is
When write instructions are executed on T00REG and T01REG in this order while the timer
(POFFCR0),0x10
(EIRH).4
(T01MOD),0xF0
(T00REG),0xE0
(T01REG),0x01
(T001CR),0x06
Page 189
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
; Selects the 16-bit timer mode and fcgck/2
; Sets the timer register (96Ps / (2/fcgck) = 0x1E0)
; Sets the timer register
; Starts TC00 and TC001 (16-bit mode)
TMP89FM42