tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 290

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

18.4 Functions
18. Serial Bus Interface (SBI)
RA001
SDA0 (Bus)
SCL0 (Bus)
SDA0 pin
INTSBI0 Interrupt request
18.4.12Slave address match detection monitor
INTSBI0 Interrupt request
received data matches the slave address setting by I2C0AR<SA> with SBI0CR1<NOACK> set at "0" and the
I
detections. SBI0SR2<AAS> remains at "0" even if a "GENERAL CALL" is received or the same slave
address as the I2C0AR<SA> set value is received.
is set to "1" after receiving the first 1-word of data. SBI0SR2<AAS> is cleared to "0" by writing data to the
SBI0DBR or reading data from the SBI0DBR.
Master A
Master B
SBI0SR2<AL>
SBI0CR2<MST>
SBI0CR2<PIN>
Access to SBI0DBR or
SBI0CR2
2
C bus mode is active (I2C0AR<ALS>="0").
Figure 18-13 Example When Master B is a Serial Bus Interface Circuit
In the slave mode, SBI0SR2<AAS> is set to "1" when the received data is "GENERAL CALL" or the
Setting SBI0CR1<NOACK> to "1" disables the subsequent slave address match and GENERAL CALL
When a serial bus interface circuit operates in the free data format (I2C0AR<ALS>= "1"), SBI0SR2<AAS>
Figure 18-14 Changes in the Slave Address Match Detection Monitor
SCL pin
SDA pin
SCL pin
SDA pin
Start condition
SA6
D7A
D7A
1
1
SA5
D6A
D6A
2
2
D5A
SA4
3
3
Slave address + Direction bit
Releasing SDA pin and SCL pin
to high level as losing arbitration.
D4A
Stop clock output
4
4
SA3
Page 276
D3A D2A D1A D0A
5
5
SA2
6
6
7
7
SA1
8
8
SA0
9
9
Writing or reading SBI0DBR
Output of an acknowledge signal
R/W
D7A’
1
D6A’
2
D5A’
TMP89FM42
3