mpc5632m Freescale Semiconductor, Inc, mpc5632m Datasheet - Page 6

• Manufacturer Part Number: mpc5632m
• Description: Mpc5634m Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

Overview
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— Three master ports, four slave ports
— 32-bit internal address bus, 64-bit internal data bus
Enhanced direct memory access (eDMA) controller
— 32 channels support independent 8-bit, 16-bit, or 32-bit single value or block transfers
— Supports variable sized queues and circular queues
— Source and destination address registers are independently configured to post-increment or remain constant
— Each transfer is initiated by a peripheral, CPU, or eDMA channel request
— Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block
Interrupt controller (INTC)
— 191 peripheral interrupt request sources
— 8 software setable interrupt request sources
— 9-bit vector
— Each interrupt source can be programmed to one of 16 priorities
— Preemption
— Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor
Frequency Modulating Phase-locked loop (FMPLL)
— Reference clock pre-divider (PREDIV) for finer frequency synthesis resolution
— Reduced frequency divider (RFD) for reducing the FMPLL output clock frequency without forcing the FMPLL
— System clock divider (SYSDIV) for reducing the system clock frequency in normal or bypass mode
— Input clock frequency range from 4 MHz to 20 MHz before the pre-divider, and from 4 MHz to 16 MHz at the
— Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz
— VCO free-running frequency range from 25 MHz to 125 MHz
— Four bypass modes: crystal or external reference with PLL on or off
— Two normal modes: crystal or external reference
— Programmable frequency modulation
— Lock detect circuitry reports when the FMPLL has achieved frequency lock and continuously monitors lock status
— Clock quality monitor (CQM) module provides loss-of-clock detection for the FMPLL reference and output
– Masters: CPU Instruction bus; CPU Load/store bus (Nexus); eDMA
– Slave: Flash; SRAM; Peripheral Bridge; calibration EBI
transfer
– Unique vector for each interrupt request source
– Provided by hardware connection to processor or read from register
– Preemptive prioritized interrupt requests to processor
– ISR at a higher priority preempts ISRs or tasks at lower priorities
– Automatic pushing or popping of preempted priority to or from a LIFO
– Ability to modify the ISR or task priority. Modifying the priority can be used to implement the Priority Ceiling
to re-lock
FMPLL input
– Triangle wave modulation
– Register programmable modulation frequency and depth
to report loss of lock conditions
– User-selectable ability to generate an interrupt request upon loss of lock
– User-selectable ability to generate a system reset upon loss of lock
clocks
– User-selectable ability to generate an interrupt request upon loss of clock
Protocol for accessing shared resources.
Preliminary—Subject to Change Without Notice
MPC5634M Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor