mpc5632m Freescale Semiconductor, Inc, mpc5632m Datasheet - Page 10

• Manufacturer Part Number: mpc5632m
• Description: Mpc5634m Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

Overview
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— Parallel Side Interface to communicate with an on-chip companion module
— Zero jitter triggering for queue 0. (Queue 0 trigger causes current conversion to be aborted and the queued
— eQADC Result Streaming. Generation of a continuous stream of ADC conversion results from a single eQADC
— Angular Decimation. The ability of the eQADC to sample an analog waveform in the time domain, perform
— Priority Based CFIFOs
— External Hardware Triggers
— Supports four external 8-to-1 muxes which can expand the input channel number from 31 to 59
Two deserial serial peripheral interface modules (DSPI)
— SPI
— Deserial serial interface (DSI)
Two enhanced serial communication interface (eSCI) modules
— UART mode provides NRZ format and half or full duplex interface
— eSCI bit rate up to 1 Mbps
— Advanced error detection, and optional parity generation and detection
— Word length programmable as 8, 9, 12 or 13 bits
— Separately enabled transmitter and receiver
— LIN support
— DMA support
— Interrupt request support
– Transmits a null message when there are no triggered CFIFOs with commands bound for external CBuffers,
conversions in the CBUFFER to be bypassed. Delay from Trigger to start of conversion s 13 system clocks + 1
ADC clock.)
command word. Controlled by two different trigger signals; one to define the rate at which results are generated
and the other to define the beginning and ending of the stream. Used to digitize waveforms during specific
time/angle windows, e.g., engine knock sensor sampling.
FIR/IIR filtering also in the time domain, but to down sample the results in the angle domain. Resulting in a time
domain filtered result at a given engine angle.
– Supports six CFIFOs with fixed priority. The lower the CFIFO number, the higher its priority. When
– Supports software and several hardware trigger modes to arm a particular CFIFO
– Generates interrupt when command coherency is not achieved
– Supports rising edge, falling edge, high level and low level triggers
– Supports configurable digital filter
– Full duplex communication ports with interrupt and DMA request support
– Supports all functional modes from QSPI subblock of QSMCM (MPC5xx family)
– Support for queues in RAM
– 6 chip selects, expandable to 64 with external demultiplexers
– Programmable frame size, baud rate, clock delay and clock phase on a per frame basis
– Modified SPI mode for interfacing to peripherals with longer setup time requirements
– LVDS option for output clock and data to allow higher speed communication
– Pin reduction by hardware serialization and deserialization of eTPU, eMIOS channels and GPIO
– 32 bits per DSPI module
– Triggered transfer control and change in data transfer control (for reduced EMI)
– Compatible with Microsecond Bus Version 1.0 downlink
or when there are triggered CFIFOs with commands bound for external CBuffers but the external CBuffers are
full
commands of distinct CFIFOs are bound for the same CBuffer, the higher priority CFIFO is always served
first.
Preliminary—Subject to Change Without Notice
MPC5634M Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor