mpc5632m Freescale Semiconductor, Inc, mpc5632m Datasheet - Page 14

• Manufacturer Part Number: mpc5632m
• Description: Mpc5634m Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

Overview
1.3.4
The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically
scheduled hard real-time systems. The INTC allows interrupt request servicing from up to 191 peripheral interrupt request
sources, plus 165 sources reserved for compatibility with other family members).
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor
is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt
request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of
interrupt request, the priority of each interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority
ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that
all tasks which share the resource can not preempt each other.
Multiple processors can assert interrupt requests to each other through software setable interrupt requests. These same software
setable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion
and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but then the ISR asserts a
software setable interrupt request to finish the servicing in a lower priority ISR. Therefore these software setable interrupt
requests can be used instead of the peripheral ISR scheduling a task through the RTOS.
The INTC provides the following features:
This device also includes a non-maskable interrupt (NMI) pin that bypasses the INTC and multiplexing logic.
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An inner data transfer loop defined by a “minor” byte transfer count
An outer data transfer loop defined by a “major” iteration count
Channel activation via one of three methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continuous transfers
— Peripheral-paced hardware requests (one per channel)
Support for fixed-priority and round-robin channel arbitration
Channel completion reported via optional interrupt requests
1 interrupt per channel, optionally asserted at completion of major iteration count
Error termination interrupts are optionally enabled
Support for scatter/gather DMA processing
Channel transfers can be suspended by a higher priority channel
356 peripheral interrupt request sources
8 software setable interrupt request sources
9-bit vector addresses
Unique vector for each interrupt request source
Hardware connection to processor or read from register
Each interrupt source can be programmed to one of 16 priorities
Preemptive prioritized interrupt requests to processor
ISR at a higher priority preempts executing ISRs or tasks at lower priorities
Automatic pushing or popping of preempted priority to or from a LIFO
Ability to modify the ISR or task priority to implement the priority ceiling protocol for accessing shared resources
Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor
Interrupt Controller
Preliminary—Subject to Change Without Notice
MPC5634M Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor