mpc5632m Freescale Semiconductor, Inc, mpc5632m Datasheet - Page 20

• Manufacturer Part Number: mpc5632m
• Description: Mpc5634m Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

Overview
For MPC5634M, the eTPU2 has been further enhanced with these features:
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— Input and output signal states visible from the host
2 independent 24-bit time bases for channel synchronization:
— First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), or by
— Second time base counter can work as a continuous angle counter, enabling angle based applications to match
— Both time bases can be exported to the eMIOS timer module
— Both time bases visible from the host
Event-triggered microengine:
— Fixed-length instruction execution in two-system-clock microcycle
— 14 KB of code memory (SCM)
— 3 KB of parameter (data) RAM (SPRAM)
— Parallel execution of data memory, ALU, channel control and flow control sub-instructions in selected
— 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value,
— Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned Multiply/MAC combinations,
Resource sharing features support channel use of common channel registers, memory and microengine time:
— Hardware scheduler works as a “task management” unit, dispatching event service routines by predefined,
— Automatic channel context switch when a “task switch” occurs, i.e., one function thread ends and another begins
— SPRAM shared between host CPU and eTPU2, supporting communication either between channels and host or
— Hardware implementation of four semaphores support coherent parameter sharing between both eTPU engines
— Dual-parameter coherency hardware support allows atomic access to two parameters by host
Test and development support features:
— Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware
— Software breakpoints
— SCM continuous signature-check built-in self test (MISC - multiple input signature calculator), runs concurrently
The scheduler priority-passing mechanism can be disabled.
A new watchdog mechanism kills threads over a programmable timeout.
A new counter allows microengine load information collection for performance analysis.
Channels 1 and 2 (besides channel 0) can be selected to control the EAC.
Timebase prescalers are now reset when the GTBE input is negated, guaranteeing synchronization with eMIOS in all
cases.
A new MISC flag indicates when an SCM signature calculation round is completed. This allows measuring of the
average MISC scan period in a real application situation.
A new channel TCCEA flag allows continuous capture even after TDLA is set, making it fully compatible with TPU
behavior.
output of second time base prescaler
angle instead of time
combinations
bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign
extension and conditional execution
and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands
host-configured priority
to service a request from other channel: channel-specific registers, flags and parameter base address are
automatically loaded for the next serviced channel
inter-channel
breakpoints and watchpoints on several conditions
with eTPU2 normal operation
Preliminary—Subject to Change Without Notice
MPC5634M Microcontroller Data Sheet, Rev. 3
Freescale Semiconductor