mpc5632m Freescale Semiconductor, Inc, mpc5632m Datasheet
mpc5632m
Related parts for mpc5632m
mpc5632m Summary of contents
Page 1
... Periodic interrupt timer (PIT) This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2008, 2009. All rights reserved. Preliminary—Subject to Change Without Notice Document Number: MPC5634M MPC5634M ...
Page 2
Overview ...
Page 3
... Yes Channels Yes 5 364 Yes Class 2+ Yes 5 MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Overview TM technology and: MPC5633M MPC5632M 1 1024 768 32-bit e200z335 32-bit e200z335 with SPE support with SPE support 40/60/80 40/60 16 bits — ...
Page 4
... Frequency modulation of system clock frequency 4 MPC5634M 4 channels Yes Yes 144 LQFP 176 LQFP 208 MAPBGA MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice MPC5633M MPC5632M 4 channels 4 channels Yes Yes Yes Yes 6 100 LQFP 100 LQFP 144 LQFP 144 LQFP ...
Page 5
On-chip bypass capacitance – Selectable slew rate and drive strength • High performance e200z335 core processor — 32-bit Power Architecture Book E programmer’s model — Variable Length Encoding Enhancements – Allows Power Architecture instruction set to be optionally encoded ...
Page 6
Overview — Three master ports, four slave ports – Masters: CPU Instruction bus; CPU Load/store bus (Nexus); eDMA – Slave: Flash; SRAM; Peripheral Bridge; calibration EBI — 32-bit internal address bus, 64-bit internal data bus • Enhanced direct memory access ...
Page 7
... For MPC5634M: 18 blocks (4 × 16 KB, 2 × 32 KB, 2 × 64 KB, 10 × 128 KB) – For MPC5633M: 14 blocks (4 × 16 KB, 2 × 32 KB, 2 × 64 KB, 6 × 128 KB) – For MPC5632M: 12 blocks (4 × 16 KB, 2 × 32 KB, 2 × 64 KB, 4 × 128 KB) — Hardware programming state machine 1. Revision 1 of the MPC5633M has a different flash memory organization: 10 blocks (2 × ...
Page 8
... For MPC5634M general purpose RAM of which 32 KB are on standby power supply — For MPC5633M general purpose RAM of which 24 KB are on standby power supply — For MPC5632M general purpose RAM of which 24 KB are on standby power supply • Boot assist module (BAM) — ...
Page 9
Double match/capture channels — Angle clock hardware support — Nexus Class 1 Debug support — Enhancements to make DMA and interrupt operation more flexible — New programmable channel mode, for increased flexibility of channel hardware — Scheduler priority-passing mechanism ...
Page 10
Overview – Transmits a null message when there are no triggered CFIFOs with commands bound for external CBuffers, or when there are triggered CFIFOs with commands bound for external CBuffers but the external CBuffers are full — Parallel Side Interface ...
Page 11
Programmable clock source: system clock or oscillator clock — Support Microsecond Bus (Timed Serial Bus - TSB) uplink Version 1.0 • Two FlexCAN — One with 32 message buffers; the second with 64 message buffers — Full implementation of ...
Page 12
Overview 1.3 MPC5634M Feature Details 1.3.1 e200z335 Core The e200z335 processor utilizes a four stage pipeline for instruction execution. The Instruction Fetch (stage 1), Instruction Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback (stage ...
Page 13
The CPU includes support for Variable Length Encoding (VLE) instruction enhancements. This enables the classic Power Architecture instruction set to be represented by a modified instruction set made up from a mixture of 16- and 32-bit instructions. This results in ...
Page 14
Overview • An inner data transfer loop defined by a “minor” byte transfer count • An outer data transfer loop defined by a “major” iteration count • Channel activation via one of three methods: — Explicit software initiation — Initiation ...
Page 15
FMPLL The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 20 MHz crystal oscillator or external clock generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication ...
Page 16
Overview — User selectable — Programmable time-out period (with 8 external bus clock resolution) • Configurable wait states (via chip selects) • 3 chip-select (Cal_CS[0], Cal_CS[2:3]) signals (Multiplexed with 2 most significant address signals) • 2 write/byte enable (WE[0:1]/BE[0:1]) signals ...
Page 17
ECSM The error correction status module provides status information regarding platform memory errors reported by error-correcting codes. 1.3.9 Flash The MPC5634M provides programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used for ...
Page 18
Overview • Byte, halfword, word and doubleword addressable • ECC performs single-bit correction, double-bit detection on 32-bit data element 1.3.11 BAM The BAM (Boot Assist Module block of read-only memory that is programmed once by Freescale and is ...
Page 19
Input Pulse Width Measurement (IPWM) — Double Action Output Compare {set flag on both matches} (DAOC) — Modulus Counter Buffered (MCB) — Output Pulse Width and Frequency Modulation Buffered (OPWFMB) • Channel features: — 24-bit registers for captured/match values ...
Page 20
Overview — Input and output signal states visible from the host • 2 independent 24-bit time bases for channel synchronization: — First time base clocked by system clock with programmable prescale division from 2 to 512 (in steps of 2), ...
Page 21
A new branch condition PRSS tells the pin state at the time when a channel (match or transition) service request occurred. • MRLEA/B can now be negated independently by microcode. • A new Engine Relative address mode allows a ...
Page 22
Overview — Including Core voltage, I/O voltage, LVI voltages, etc. • An internal bandgap reference to allow absolute voltage measurements • 4 pairs of differential analog input channels — Programmable pull-up/pull-down resistors on each differential input for biasing and sensor ...
Page 23
Programmable inter-frame gap in continuous mode — Bit source selection allows microsecond bus downlink with command or data frames bits — Microsecond bus dual receiver mode • Combined serial interface (CSI) configuration where the DSPI operates ...
Page 24
Overview — eTPU_A and eMIOS output channels — Memory-mapped register in the DSPI • Destinations for the deserialized data: — eTPU_A and eMIOS input channels — SIU External Interrupt Request inputs — Memory-mapped register in the DSPI • Deserialized data ...
Page 25
FlexCAN The MPC5634M MCU contains two controller area network (FlexCAN) blocks. The FlexCAN module is a communication controller implementing the CAN protocol according to Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a ...
Page 26
Overview 1.3.18.1 Peripheral Interrupt Timer (PIT) The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has no external input or output pins and is intended to be used to provide system ‘tick’ ...
Page 27
IEEE-ISTO 5001-2003 standard. The development support provided includes program trace and run-time access to the MCUs internal memory map and access to the ...
Page 28
Overview – CPU only – Detects ‘equal’ and ‘not equal’ – Byte, half word, word (naturally aligned) This feature is imprecise due to CPU pipelining. — Subset of Power Architecture Book E software debug facilities with OnCE block (Nexus class ...
Page 29
MPC5634M Series Architecture 1.4.1 Block Diagram Figure 1 shows a top-level block diagram of the MPC5634M series. Test Controller JTAG JTAG Port Nexus Port Nexus NMI eTPU NMI SIU critical Interrupt Requests from Peripheral Blocks & eDMA Clocks CQM ...
Page 30
Pinout and Signal Description Block E200z3 core Flash memory RAM (random-access memory) Calibration bus DMA (direct memory access) DSPI (deserial serial peripheral interface) eMIOS (enhanced modular input-output system) Provides the functionality to generate or measure events eQADC (enhanced queued analog-to-digital ...
Page 31
LQFP Pinout (all 100-pin devices) Figure 2 shows the pinout for the 100-pin LQFP. AN[11] / ANZ AN[39] / AN[10] / ANY AN[38] / AN[8] / ANW eTPU_A[31] / DSPI_C_PCS[4] / eTPU_A[13] / GPIO[145] eTPU_A[30] / DSPI_C_PCS[3] / ...
Page 32
Pinout and Signal Description 2.2 144 LQFP Pinout (all 144-pin devices) Figure 3 shows the pinout for the 144-pin LQFP. 1 AN[18] 2 AN[17] 3 AN[16] 4 AN[11] / ANZ 5 AN[9] / ANX 6 VDDA 7 VSSA 8 AN[39] ...
Page 33
LQFP Pinout (MPC5634M) Figure 4 shows the 176-pin LQFP pinout for the MPC5634M (1536 KB flash memory). AN[18] 1 AN[17] 2 AN[16] 3 AN[11] / ANZ 4 AN[9] / ANX 5 VDDA 6 VSSA 7 AN[39] / AN[10] ...
Page 34
Pinout and Signal Description 2.4 176 LQFP Pinout (MPC5633M) Figure 5 shows the pinout for the 176-pin LQFP for the MPC5633M (1024 KB flash memory). AN[18] 1 AN[17] 2 AN[16] 3 AN[11] / ANZ 4 AN[9] / ANX 5 VDDA ...
Page 35
MAPBGA208 Ballmap (MPC5634M) Figure 6 shows the 208-pin MAPBGA ballmap for the MPC5634M (1536 KB flash memory) as viewed from above VSS AN9 AN11 VDDA1 VSSA1 A VDD VSS AN38 AN21 AN0 B VSTBY ...
Page 36
MAPBGA208 Ballmap (MPC5633M only) Figure 7 shows the 208-pin MAPBGA ballmap for the MPC5633M (1024 KB flash memory) as viewed from above VSS AN9 AN11 VDDA1 VSSA1 A VDD VSS AN38 AN21 AN0 B ...
Page 37
Signal Summary t 1 Name Function GPIO[98] GPIO GPIO[99] GPIO GPIO[206] GPIO GPIO[207] GPIO RESET External Reset Input RSTOUT External Reset Output PLLREF FMPLL Mode Selection IRQ[4] External Interrupt Request ETRIG[2] eQADC Trigger Input GPIO[208] GPIO BOOTCFG1 Boot Config. ...
Page 38
Table 3. MPC563xM Signal Properties (continued) 1 Name Function 18 CAL_ADDR[18] Calibration Address Bus 10 MDO[2] Nexus Msg Data Out 18 CAL_ADDR[19] Calibration Address Bus 10 MDO[3] Nexus Msg Data Out CAL_ADDR[20:27] Calibration Address Bus MDO[4:11] Nexus Msg Data Out ...
Page 39
Table 3. MPC563xM Signal Properties (continued) 1 Name Function CAL_RD_WR Calibration Read/Write CAL_TS_ALE Calibration Transfer Start Address Latch Enable CAL_WE_BE Calibration Write Enable [0:1] Byte Enable 18 EVTI Nexus Event In eTPU_A[2] eTPU A Ch. GPIO[231] GPIO 18 EVTO Nexus ...
Page 40
Table 3. MPC563xM Signal Properties (continued) 1 Name Function 20 TDI JTAG Test Data Input eMIOS[5] eMIOS Ch. GPIO[232] GPIO 20 TDO JTAG Test Data Output eMIOS[6] eMIOS Ch. GPIO[228] GPIO TMS JTAG Test Mode Select Input JCOMP JTAG TAP ...
Page 41
Table 3. MPC563xM Signal Properties (continued) 1 Name Function DSPI_B_SIN DSPI_B Data Input DSPI_C_PCS[2] DSPI_C Periph Chip Select GPIO[103] GPIO DSPI_B_SOUT DSPI_B Data Output DSPI_C_PCS[5] DSPI_C Periph Chip Select GPIO[104] GPIO DSPI_B_PCS[0] DSPI_B Periph Chip Select GPIO[105] GPIO DSPI_B_PCS[1] DSPI_B ...
Page 42
Table 3. MPC563xM Signal Properties (continued) 1 Name Function AN[7] Single Ended Analog Input DAN3- Negative Terminal Diff. Input AN[8] See AN[38]-AN[8]-ANW AN[9] Single Ended Analog Input ANX External Multiplexed Analog Input AN[10] See AN[39]-AN[10]-ANY AN[11] Single Ended Analog Input ...
Page 43
Table 3. MPC563xM Signal Properties (continued) 1 Name Function AN[32] Single Ended Analog Input AN[33] Single Ended Analog Input AN[34] Single Ended Analog Input AN[35] Single Ended Analog Input AN[36] Single Ended Analog Input AN[37] Single Ended Analog Input AN[38]-AN[8]- ...
Page 44
Table 3. MPC563xM Signal Properties (continued) 1 Name Function eTPU_A[6] eTPU_A Ch. eTPU_A[18] eTPU_A Ch. DSPI_B_SCK_LVDS+ DSPI_B Clock LVDS+ GPIO[120] GPIO eTPU_A[7] eTPU_A Ch. eTPU_A[19] eTPU_A Ch. DSPI_B_SOUT_LVDS- DSPI_B Data Output LVDS- eTPU_A[6] eTPU_A Ch. GPIO[121] GPIO eTPU_A[8] eTPU_A Ch. ...
Page 45
Table 3. MPC563xM Signal Properties (continued) 1 Name Function eTPU_A[18] eTPU_A Ch. GPIO[132] GPIO eTPU_A[19] eTPU_A Ch. GPIO[133] GPIO eTPU_A[20] eTPU_A Ch. IRQ[8] External Interrupt Request GPIO[134] GPIO eTPU_A[21] eTPU_A Ch. IRQ[9] External Interrupt Request GPIO[135] GPIO eTPU_A[22] eTPU_A Ch. ...
Page 46
Table 3. MPC563xM Signal Properties (continued) 1 Name Function eTPU_A[29] eTPU_A Ch. (Output Only) DSPI_C_PCS[2] DSPI_C Periph Chip Select GPIO[143] GPIO eTPU_A[30] eTPU_A Ch. DSPI_C_PCS[3] DSPI_C Periph Chip Select eTPU_A[11] eTPU_A Ch. GPIO[144] GPIO eTPU_A[31] eTPU_A Ch. DSPI_C_PCS[4] DSPI_C Periph ...
Page 47
Table 3. MPC563xM Signal Properties (continued) 1 Name Function 26 eMIOS[12] eMIOS Ch. DSPI_C_SOUT DSPI C Data Output eTPU_A[27] eTPU_A Ch. GPIO[191] GPIO eMIOS[13] eMIOS Ch. GPIO[192] GPIO eMIOS[14] eMIOS Ch. IRQ[0] External Interrupt Request eTPU_A[29] eTPU_A Ch. GPIO[193] GPIO ...
Page 48
Table 3. MPC563xM Signal Properties (continued) 1 Name Function VDDA1 Analog Power Input for eQADC VSSA1 Analog Ground Input for eQADC 31 VSSA Analog Ground Input for eQADC VDDREG Voltage Regulator Supply VDD Internal Logic Supply Input VSS Ground 32 ...
Page 49
Table 3. MPC563xM Signal Properties (continued) 1 Name Function VDDE5 I/O Supply Input 34 VDDEH6a I/O Supply Input VDDEH6b VDDEH6 I/O Supply Input VSSE6a I/O Ground Input VSSE6b VDDEH7 I/O Supply Input VDDE7 I/O Supply Input VSSE7 I/O Ground Input ...
Page 50
From the user point of view this is an output pad; to implement the CAN protocol this pad must also implement the input direction. 23 The function and state of the CAN_A and eSCI_A pins after execution of the ...
Page 51
Electrical Characteristics This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the MPC5634M series of MCUs. The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These ...
Page 52
Electrical Characteristics Table 4. Absolute Maximum Ratings Symbol VRL SSA voltage SSPLL SS SSPLL voltage I SR Maximum DC digital input MAXD 13 current I SR ...
Page 53
Thermal Characteristics Table 5. Thermal Characteristics for 100-pin LQFP Symbol R CC Junction-to-Ambient, Natural θJA Convection R CC Junction-to-Ambient, Natural θJA Convection R CC Junction-to-Ambient θJMA R CC Junction-to-Ambient θJMA R CC Junction-to-Board θ Junction-to-Case (Top) θJCtop ...
Page 54
Electrical Characteristics 2 Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package. 3 Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package. 4 ...
Page 55
Table 8. Thermal Characteristics for 208-pin MAPBGA Symbol R CC Junction-to-ambient θJMA R CC Junction-to-board θ Junction-to-case θJC Ψ CC Junction-to-package top natural JT convection 1 Thermal characteristics are targets based on simulation that are subject to change ...
Page 56
Electrical Characteristics As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal ...
Page 57
power dissipation in the package (W) D The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of ...
Page 58
Electrical Characteristics 3.4 Electromagnetic Static Discharge (ESD) Characteristics Symbol — SR ESD for Human Body Model (HBM HBM circuit description C SR — SR ESD for field induced charge Model (FDCM) — SR Number of pulses per pin ...
Page 59
ID Name Parameter 1 Vbg Nominal bandgap voltage reference 1a — Untrimmed bandgap reference voltage 1b — Trimmed bandgap reference voltage ( °C) 1c — Bandgap reference temperature variation 1d — Bandgap reference supply voltage variation 2 Vdd1p2 ...
Page 60
Electrical Characteristics Table 12. PMC Electrical Characteristics (continued) ID Name Parameter 5 Vdd3p3 Nominal 3.3 V supply internal regulator DC output voltage 5a — Nominal 3.3 V supply internal regulator DC output voltage variation before band-gap trim 5b — Nominal ...
Page 61
Table 12. PMC Electrical Characteristics (continued) ID Name Parameter 8a — Variation of LVI for rising 5 V VDDREG supply before band gap trim 8b — Variation of LVI for rising 5 V VDDREG supply after band gap trim 8c ...
Page 62
Electrical Characteristics Table 14. Power Sequence Pin States (PAD_MSR_HV / PAD_SSR_HV / PAD_MULTV_HV) V LOW V V 3.7 DC Electrical Specifications Symbol Parameter V SR Core supply DD voltage V SR I/O supply DDE voltage V SR I/O supply DDEH ...
Page 63
Table 15. DC Electrical Specifications Symbol Parameter Flash read FLASH voltage V SR SRAM standby STBY voltage V SR Voltage DDREG regulator supply 8 voltage V SR Clock DDPLL synthesizer operating voltage ...
Page 64
Electrical Characteristics Table 15. DC Electrical Specifications Symbol Parameter V SR Multi-voltage IH_HS pad I/O input high voltage in high-swing 14 mode V CC Slow/medium OL_S multi-voltage pad I/O output low voltage V CC Fast pad I/O OL_F output low ...
Page 65
Table 15. DC Electrical Specifications Symbol Parameter V CC Low-Swing-Mod HYS_LS e Multi-Voltage I/O Input Hysteresis I SR Operating DD I current 1.2 V DDSTBY I supplies DDSTBY150 I DDPLL low-power DDSLOW DD I mode operating DDSTOP ...
Page 66
Electrical Characteristics Table 15. DC Electrical Specifications Symbol Parameter I SR Slow/medium ACT_S I/O weak pull up/down 21 current SR Fast I/O weak I pull up/down ACT_F 21 current I CC Multi-voltage ACT_MV_PU pad weak pullup current I CC Multivoltage ...
Page 67
Table 15. DC Electrical Specifications Symbol Parameter C CC Input IN capacitance (digital pins Input IN_A capacitance (analog pins Input IN_M capacitance (digital and analog pins R SR Weak PUPD200K Pull-Up/Down Resistance 200 kΩ Option R ...
Page 68
Electrical Characteristics only available in the calibration package. FLASH 8 Regulator is functional, with derated performance, with supply voltage down to 4 Multi-voltage pads (type pad_multv_hv) cannot be below 4.5 V when in low-swing mode. ...
Page 69
Table 16. I/O Pad Average I No. Pad Type Symbol 1 Slow I DRV_SSR_HV Medium I DRV_MSR_HV Fast I DRV_FC Multi-V I ...
Page 70
Electrical Characteristics 3.8.1 I/O Pad VRC33 Current Specifications The power consumption of the VRC33 supply is dependent on the usage of the pins on all I/O segments. The power consumption is the sum of all output pin V from Table ...
Page 71
Pad Spec Symbol Type Fast I DRV_FC These are typical values that are estimated from simulation and not tested. Currents apply to output pins only. 2 All loads are lumped. 3.8.2 ...
Page 72
Electrical Characteristics Table 19. DSPI LVDS Pad Specification 8 Propagation delay (Low to High) 9 Propagation delay (High to Low) 10 Delay (H/L), sync Mode 11 Delay Normal (High/Low) 12 Diff Skew Itphla-tplhbI or Itplhb-tphlaI 13 Trans. Line ...
Page 73
Table 20. PLLMRFM Electrical Specifications ( DDPLL Symbol C CC CLKOUT JITTER period 7,8,9,10 jitter t CC Crystal start-up time cst V CC EXTAL input high voltage IHEXT V CC EXTAL input low ...
Page 74
Electrical Characteristics 10 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C either (depending on whether center spread or down spread modulation is enabled This value ...
Page 75
Table 22. eQADC Conversion Specifications (operating) (continued) Symbol GAINWC CC Full scale gain error with calibration I CC Disruptive input injection current INJ E CC Incremental error due to injection current INJ TUE8 CC Total unadjusted error (TUE ...
Page 76
Electrical Characteristics 3.13 Flash Memory Electrical Characteristics Table 24. Flash Program and Erase Specifications Symbol Parameter t CC Double word (64 bits) program PRGDW t CC Bank program (512 KB) PRGBK t CC Sector erase (8 KB) ES8K t CC ...
Page 77
AC Specifications 3.14.1 Pad AC Specifications Table 25. Pad AC Specifications (5.0 V, 1.8 V) Output Delay (ns) Low-to-High / High-to-Low Name Min 4.7/4.2 14/13 6,7,8 Medium 8.6/14 18/26 64/77 89/101 7.4/6.8 9.2/8.1 8,11 Slow 26/26 31/31 137/139 163/167 ...
Page 78
Electrical Characteristics 6 In high swing mode, high/low swing pad Vol and Voh values are the same as those of the slew controlled output pads 7 Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown. 8 Output ...
Page 79
Table 26. Pad AC Specifications (3.3 V, 3.3 V) Output Delay (ns) Low-to-High / High-to-Low Pad Type Min 7,11 Multi-V (Low Swing Mode) 12 pad_i_hv 0.5/0.5 pull_hv NA 1 These are worst case values that are estimated from simulation and ...
Page 80
Electrical Characteristics Pad Data Input Pad Output 3.15 AC Timing 3.15.1 IEEE 1149.1 Interface Timing Table 27. JTAG Pin AC Electrical Characteristics Num Symbol JCYC JDC TCKRISE ...
Page 81
Table 27. JTAG Pin AC Electrical Characteristics Num Symbol BSDVZ BSDHZ BSDST BSDHT 1 JTAG timing specified Low-Swing mode ...
Page 82
Electrical Characteristics TCK TMS, TDI TDO TCK JCOMP Figure 10. JTAG Test Access Port Timing 9 Figure 11. JTAG JCOMP Timing MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Freescale ...
Page 83
TCK 11 Output Signals 12 Output Signals Input Signals 3.15.2 Nexus Timing Num Symbol MCKO Cycle Time MCYC Absolute Minimum MCKO Cycle Time MCYC MCKO Duty Cycle MDC ...
Page 84
Electrical Characteristics Table 28. Nexus Debug Port Timing Num Symbol TDI Data Setup Time NTDIS TDI Data Hold Time NTDIH TMS Data Setup Time NTMSS TMS Data Hold ...
Page 85
TCK EVTI EVTO Figure 14. Nexus Event Trigger and Test Clock Timings TCK TMS, TDI TDO Freescale Semiconductor Figure 15. Nexus TDI, TMS, TDO Timing MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without ...
Page 86
Electrical Characteristics 3.15.3 Calibration Bus Interface Timing Table 29. Calibration Bus Operation Timing Num Symbol CLKOUT Period CLKOUT duty cycle CDC CLKOUT rise time CRT CLKOUT fall ...
Page 87
Vol_f CLKOUT CLKOUT 5 OUTPUT VDDE/2 BUS 5 OUTPUT VDDE/2 SIGNAL OUTPUT SIGNAL Freescale Semiconductor Voh_f 3 4 Figure 16. CLKOUT Timing 6 6 Figure 17. Synchronous Output Timing MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice ...
Page 88
Electrical Characteristics CLKOUT INPUT BUS INPUT SIGNAL VDDE/2 ipg_clk CLKOUT ALE TS A/D 88 VDDE/2 7 VDDE/2 7 Figure 18. Synchronous Input Timing DATA ADDR 9 10 Figure 19. ALE Signal Timing MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to ...
Page 89
Timing Num Symbol eMIOS Input Pulse Width MIPW eMIOS Output Pulse Width MOPW 1 eMIOS timing specified at f SYS 50 pF with SRC = 0b00. 3.15.5 DSPI Timing Num Symbol Characteristic ...
Page 90
Electrical Characteristics Num Symbol Characteristic Master (MTFE = 0) Slave Master (MTFE = 1, CPHA = 0) Master (MTFE = 1, CPHA = SUO Master (MTFE = 0) Slave Master (MTFE = ...
Page 91
PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) 9 SIN First Data First Data SOUT Figure 20. DSPI Classic SPI Timing - Master, CPHA = 0 PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) SIN SOUT Figure 21. DSPI Classic SPI ...
Page 92
Electrical Characteristics 2 SS SCK Input (CPOL=0) SCK Input (CPOL=1) 5 First Data SOUT 9 First Data SIN Figure 22. DSPI Classic SPI Timing - Slave, CPHA = 0 SS SCK Input (CPOL=0) SCK Input (CPOL= SOUT SIN ...
Page 93
PCSx 2 SCK Output (CPOL=0) SCK Output (CPOL=1) 9 SIN First Data 12 SOUT First Data Figure 24. DSPI Modified Transfer Format Timing - Master, CPHA = 0 PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) SIN SOUT Figure 25. DSPI ...
Page 94
Electrical Characteristics 2 SS SCK Input (CPOL=0) SCK Input (CPOL=1) 5 First Data SOUT 9 First Data SIN Figure 26. DSPI Modified Transfer Format Timing - Slave, CPHA =0 SS SCK Input (CPOL=0) SCK Input (CPOL= SOUT SIN ...
Page 95
SSI Timing Table 32. eQADC SSI Timing Characteristics (pads at 3 5.0 V) CLOAD = 25pF on all outputs. Pad drive strength set to maximum. Num Symbol FCK Frequency FCK 1 t ...
Page 96
Mechanical Outline Drawings 4 Mechanical Outline Drawings 4.1 100 LQFP 96 MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Freescale Semiconductor ...
Page 97
Figure 30. 100 LQFP Package Mechanical Drawing (part 1) Freescale Semiconductor MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Mechanical Outline Drawings 97 ...
Page 98
Mechanical Outline Drawings Figure 31. 100 LQFP Package Mechanical Drawing (part 2) 98 MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Freescale Semiconductor ...
Page 99
Figure 32. 100 LQFP Package Mechanical Drawing (part 3) Freescale Semiconductor MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Mechanical Outline Drawings 99 ...
Page 100
Mechanical Outline Drawings 4.2 144 LQFP Figure 33. 144 LQFP Package Mechanical Drawing (part 1) 100 MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Freescale Semiconductor ...
Page 101
Figure 34. 144 LQFP Package Mechanical Drawing (part 2) Freescale Semiconductor MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Mechanical Outline Drawings 101 ...
Page 102
Mechanical Outline Drawings Figure 35. 144 LQFP Package Mechanical Drawing (part 3) 102 MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Freescale Semiconductor ...
Page 103
LQFP Figure 36. 176 LQFP Package Mechanical Drawing (part 1) Freescale Semiconductor MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Mechanical Outline Drawings 103 ...
Page 104
Mechanical Outline Drawings Figure 37. 176 LQFP Package Mechanical Drawing (part 2) 104 MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Freescale Semiconductor ...
Page 105
Figure 38. 176 LQFP Package Mechanical Drawing (part 3) Freescale Semiconductor MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Mechanical Outline Drawings 105 ...
Page 106
Mechanical Outline Drawings 4.4 208 MAPBGA Figure 39. 208 MAPBGA Package Mechanical Drawing (part 1) 106 MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Freescale Semiconductor ...
Page 107
Figure 40. 208 MAPBGA Package Mechanical Drawing (part 2) Freescale Semiconductor MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Mechanical Outline Drawings 107 ...
Page 108
Ordering Information 5 Ordering Information Table 35 shows the orderable part numbers for the MPC5634M series. Part Number SPC5632MF0MLQA6 SPC5632MF0MLLA6 SPC5632MF0MLQA4 SPC5632MF0MLLA4 SPC5633MF0MMGA8 SPC5633MF0MLUA8 SPC5633MF0MLQA8 SPC5633MF0MLLA8 SPC5633MF0MMGA6 SPC5633MF0MLUA6 SPC5633MF0MLQA6 SPC5633MF0MLLA6 SPC5633MF0MLQA4 SPC5633MF0MLLA4 SPC5634MF0MMGA8 SPC5634MF0MLUA8 SPC5634MF0MLQA8 SPC5634MF0MMGA6 SPC5634MF0MLUA6 SPC5634MF0MLQA6 108 Table ...
Page 109
Example code: Qualification Status PowerPC Core Automotive Platform Flash Size (core dependent) Temperature Spec. Maximum Frequency Qualification Status status S = Auto qualified status Automotive Platform 56 = PPC ...
Page 110
Document Revision History 6 Document Revision History Table 36 summarizes revisions to this document. Revision Date Rev. 1 4/2008 Initial release Rev. 2 12/2008 110 Table 36. Revision History Substantive changes • Maximum amount of flash increased from 1 MB ...
Page 111
Revision Date Rev. 3 2/2009 Freescale Semiconductor Table 36. Revision History (continued) Substantive changes • Electrical characteristics updated — Flash memory electrical characteristics updated for LC flash. — Power management control (PMC) and Power on Reset (POR) specifications updated. — ...
Page 112
... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. All rights reserved. MPC5634M Microcontroller Data Sheet, Rev. 3 Preliminary—Subject to Change Without Notice Freescale Semiconductor ...