mpc5632m Freescale Semiconductor, Inc, mpc5632m Datasheet - Page 19

• Manufacturer Part Number: mpc5632m
• Description: Mpc5634m Microcontroller Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

1.3.13
The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, eTPU2 processes
instructions and real-time input events, performs output waveform generation, and accesses shared data without host
intervention. Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful
timer subsystem is formed by combining the eTPU2 with its own instruction and data RAM. High-level assembler/compiler
and documentation allows customers to develop their own functions on the eTPU2.
MPC5634M devices feature the second generation of the eTPU, called eTPU2. Enhancements of the eTPU2 over the standard
eTPU include:
The eTPU2 includes these distinctive features:
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
•
•
•
— Input Pulse Width Measurement (IPWM)
— Double Action Output Compare {set flag on both matches} (DAOC)
— Modulus Counter Buffered (MCB)
— Output Pulse Width and Frequency Modulation Buffered (OPWFMB)
Channel features:
— 24-bit registers for captured/match values
— 24-bit internal counter
— Global prescaler
— Selectable time base
— Can generate its own time base
Three 24-bit wide counter buses
— Counter bus A can be driven by channel 23
— Counter bus B and C are driven by channels 0 and 8, respectively
— Counter bus A can be shared among all channels. Channels 0 to 6 and 8 to 15 can share counter buses B and C,
Shared time bases with the eTPU through the counter buses
Synchronization among internal and external time bases
Shadow FLAG register
State of block can be frozen for debug purposes
The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input
[TCRCLK]) now have an option to run at full system clock speed or system clock / 2
Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this
enhancement, the transition detection latches (TDL1 and TDL2) can now be independently negated by microcode.
Added a new User Programmable Channel Mode: the blocking, enabling, service request and capture characteristics
of this channel mode can be programmed via microcode
Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by CHAN. They can
also be requested simultaneously at the same instruction.
Channel Flags 0 and 1 can now be tested for branching, besides selecting the entry point
Channel digital filters can be bypassed
32 channels, each channel is associated with one input and one output signal
— Enhanced input digital filters on the input pins for improved noise immunity.
— Identical, orthogonal channels: each channel can perform any time function. Each time function can be assigned
— Each channel has an event mechanism which supports single and double action functionality in various
respectively (channel 7 is not implemented).
to more than one channel as a given time, so each signal can have any functionality.
combinations. It includes two 24-bit capture registers, two 24-bit match registers, 24-bit greater-equal and
equal-only comparators
eTPU2
Preliminary—Subject to Change Without Notice
MPC5634M Microcontroller Data Sheet, Rev. 3
Overview
19