IDT723642L15PF IDT, Integrated Device Technology Inc, IDT723642L15PF Datasheet - Page 5

• Manufacturer Part Number: IDT723642L15PF
• Description: IC FIFO SYNC 2048X36 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT723642L15PF

• Function: Synchronous
• Memory Size: 72K (2K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Configuration: Dual
• Density: 72Kb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 1Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 723642L15PF

PIN DESCRIPTIONS (CONTINUED)
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Symbol
ORA
ORB
RST1
RST2
W/RA
W/RB
Output Ready
Flag
Output Ready
Flag
FIFO1 Reset
FIFO2 Reset
Port A Write/
Read Select
Port B Write/
Read Select
Name
(Port A)
(Port B)
I/O
O
O
I
I
I
I
ORA is synchronized to the LOW-to-HIGH transition of CLKA. When ORA is LOW, FIFO2 is
empty and reads from its memory are disabled. Ready data is present on the output register
of FIFO2 when ORA is HIGH. ORA is forced LOW when FlFO2 is reset and goes HIGH on the
third LOW-to-HIGH transition of CLKA after a word is loaded to empty memory.
ORB is synchronized to the LOW-to-HIGH transition of CLKB. When ORB is LOW, FlFO1 is
empty and reads from its memory are disabled. Ready data is present on the output register of FIFO1
when ORB is HIGH. ORB is forced LOW when FIFO1 is reset and goes HIGH on the third LOW-to-
HIGH transition of CLKB after a word is loaded to empty memory.
To reset FIFO1, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while RST1 is LOW. The LOW-to-HIGH transition of RST1 latches the status of FS0
and FS1 for AFA and AEB offset selection. FIFO1 must be reset upon power up before data is
written to its RAM.
To reset FIFO2, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while RST2 is LOW. The LOW-to-HIGH transition of RST2 latches the status of FS0
and FS1 for AFB and AEA offset selection. FIFO2 must be reset upon power up before data is
written to its RAM.
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is LOW.
5
Description
COMMERCIAL TEMPERATURE RANGE