IDT723642L15PF IDT, Integrated Device Technology Inc, IDT723642L15PF Datasheet - Page 11

• Manufacturer Part Number: IDT723642L15PF
• Description: IC FIFO SYNC 2048X36 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT723642L15PF

• Function: Synchronous
• Memory Size: 72K (2K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Configuration: Dual
• Density: 72Kb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 1Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 723642L15PF

Selects and Write/Read selects are only for enabling write and read
operations and are not related to high-impedance control of the data
outputs. If a port enable is LOW during a clock cycle, the port’s Chip Select
and Write/Read select may change states during the setup and hold time
window of the cycle.
automatically sent to the FIFO output register automatically by the LOW-to-HIGH
transition of the port clock that sets the Output Ready flag HIGH. When the Output
Ready flag is HIGH, subsequent data is clocked to the output registers only when
a FIFO read is selected using the port’s Chip Select, Write/Read select, Enable,
and Mailbox select.
SYNCHRONIZED FIFO FLAGS
stages. This is done to improve flag-signal reliability by reducing the
probability of metastable events when CLKA and CLKB operate asynchro-
nously to one another. ORA, AEA, IRA, and AFA are synchronized to CLKA.
ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show
the relationship of each port flag to FIFO1 and FIFO2.
OUTPUT READY FLAGS (ORA, ORB)
reads data from its array. When the Output Ready flag is HIGH, new data
is present in the FIFO output register. When the Output Ready flag is LOW,
the previous data word is present in the FIFO output register and attempted FIFO
reads are ignored.
TABLE 3 — PORT B ENABLE FUNCTION TABLE
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
TABLE 2 — PORT A ENABLE FUNCTION TABLE
CSA
CSB
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
The setup and hold time constraints to the port Clocks for the port Chip
When a FIFO Output Ready flag is LOW, the next word written is
Each FIFO is synchronized to its port clock through at least two flip-flop
The Output Ready flag of a FIFO is synchronized to the port clock that
W/RA
W/RB
H
H
H
X
L
L
L
L
X
H
H
H
H
L
L
L
ENA
ENB
X
H
H
H
H
L
L
L
H
H
H
H
X
L
L
L
MBA
MBB
X
X
H
H
H
L
L
L
H
H
H
X
X
L
L
L
CLKA
CLKB
X
X
↑
↑
X
↑
X
↑
X
X
↑
↑
X
↑
X
↑
Data A (A0-A35) I/O
Data B (B0-B35) I/O
High-Impedance
High-Impedance
11
Output
Output
Output
Output
its output register. The state machine that controls an Output Ready flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is empty, empty+1, or empty+2. From the time a word is written
to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles
of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag
is LOW if a word in memory is the next data to be sent to the FlFO output register
and three cycles of the port Clock that reads data from the FIFO have not elapsed
since the time the word was written. The Output Ready flag of the FIFO remains
LOW until the third LOW-to-HIGH transition of the synchronizing clock occurs,
simultaneously forcing the Output Ready flag HIGH and shifting the word to the
FIFO output register.
begins the first synchronization cycle of a write if the clock transition occurs at
time t
be the first synchronization cycle (see Figures 8 and 9 for ORA and ORB timing
diagrams).
INPUT READY FLAGS (IRA, IRB)
data to its array. When the Input Ready flag is HIGH, a memory location is free
in the FIFO to receive new data. No memory locations are free when the Input
Ready flag is LOW and attempted writes to the FIFO are ignored.
state machine that controls an Input Ready flag monitors a write pointer and read
pointer comparator that indicates when the FlFO memory status is full, full-1, or
Input
Input
Input
Output
Output
Output
Output
Input
Input
Input
A FIFO read pointer is incremented each time a new word is clocked to
A LOW-to-HIGH transition on an Output Ready flag synchronizing clock
SKEW1
The Input Ready flag of a FlFO is synchronized to the port clock that writes
Each time a word is written to a FIFO, its write pointer is incremented. The
or greater after the write. Otherwise, the subsequent clock cycle can
COMMERCIAL TEMPERATURE RANGE
Mail2 read (set MBF2 HIGH)
Mail1 read (set MBF1 HIGH)
PORT FUNCTION
PORT FUNCTION
FIFO1 write
FIFO2 read
Mail1 write
FIFO2 write
FIFO1 read
Mail2 write
None
None
None
None
None
None
None
None