IDT723642L15PF IDT, Integrated Device Technology Inc, IDT723642L15PF Datasheet - Page 20

• Manufacturer Part Number: IDT723642L15PF
• Description: IC FIFO SYNC 2048X36 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT723642L15PF

• Function: Synchronous
• Memory Size: 72K (2K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Configuration: Dual
• Density: 72Kb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 1Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 723642L15PF

B0 - B35
CLKA
CLKB
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
NOTE:
1. t
NOTES:
1. t
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
A0 -A35
ENA
AEB
ENB
CLKB edge is less than t
and rising CLKB edge is less than t
CLKA
W/RA
CLKB
W/RB
SKEW1
SKEW2
MBB
MBA
ORA
CSB
ENB
CSA
ENA
IRB
X1 Words in FIFO1
is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
LOW
LOW
LOW
HIGH
FIFO2 FULL
LOW
LOW
Previous Word in FIFO2 Output Register
t
CLKH
t
ENS2
SKEW1
t
CLK
, then IRB may transition HIGH one CLKB cycle later than shown.
t
ENS2
t
CLKL
SKEW2
Figure 11. IRB Flag Timing and First Available Write when FIFO2 is Full
, then AEB may transition HIGH one CLKB cycle later than shown.
t
ENH
t
SKEW2
Figure 12. Timing for AEB
t
SKEW1
(1)
t
t
ENH
A
(1)
1
1
t
CLKH
AEB
AEB
AEB
AEB when FIFO1 is Almost-Empty
t
CLK
20
t
CLKL
2
t
PAE
2
Next Word From FIFO2
t
PIR
t
t
ENS2
ENS2
t
DS
COMMERCIAL TEMPERATURE RANGE
To FIFO2
(X1+1) Words in FIFO1
Wriite
t
ENS2
t
t
t
t
PIR
ENH
ENH
DH
t
ENH
t
PAE
3022 drw 13
3022 drw 14