IDT723642L15PF IDT, Integrated Device Technology Inc, IDT723642L15PF Datasheet - Page 14

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IDT723642L15PF

Manufacturer Part Number
IDT723642L15PF
Description
IC FIFO SYNC 2048X36 120QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet

Specifications of IDT723642L15PF

Function
Synchronous
Memory Size
72K (2K x 36)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
120-TQFP, 120-VQFP
Configuration
Dual
Density
72Kb
Access Time (max)
10ns
Word Size
36b
Organization
1Kx36x2
Sync/async
Synchronous
Expandable
No
Bus Direction
Bi-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
400mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
120
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
723642L15PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT723642L15PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT723642L15PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. t
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
FS1,FS0
FS1,FS0
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
NOTE:
1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
A0 - A35
rising edge of CLKB is less than t
SKEW1
CLKA
CLKB
MBF1
CLKB
RST1
CLKA
RST1,
RST2
ORB
AFA
AEB
ENA
IRA
IRA
IRB
is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and
4
Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
0,0
t
RSTS
t
FSS
t
FSH
SKEW1
t
t
t
RSF
RSF
RSF
Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight
1
, then IRB may transition HIGH one CLKB cycle later than shown.
t
2
PIR
t
PIR
AFA Offset
t
DS
(Y1)
t
t
DH
ENS2
14
AEB Offset
(X1)
t
FSS
t
POR
t
ENH
AFB Offset
(Y2)
0,1
t
RSTH
t
FSH
AEA Offset
COMMERCIAL TEMPERATURE RANGE
(X2)
(1)
1
t
SKEW1
First Word to FIFO1
(1)
t
PIR
2
t
PIR
3022 drw 05
3022 drw 04

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