IDT723642L15PF IDT, Integrated Device Technology Inc, IDT723642L15PF Datasheet - Page 4

• Manufacturer Part Number: IDT723642L15PF
• Description: IC FIFO SYNC 2048X36 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT723642L15PF

• Function: Synchronous
• Memory Size: 72K (2K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Configuration: Dual
• Density: 72Kb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 1Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 723642L15PF

PIN DESCRIPTIONS
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Symbol
A0-A35
AEA
AEB
AFA
AFB
B0 - B35
CLKA
CLKB
CSA
CSB
ENA
ENB
FS1, FS0
IRA
IRB
MBA
MBF1
MBF2
MBB
Port A Almost-
Empty Flag
Port B Almost-
Empty Flag
Port A Almost-
Full Flag
Port B Almost-
Full Flag
Port B Data
Port A Clock
Port B Clock
Port A Chip
Select
Port B Chip
Select
Port A Enable
Port B Enable
Flag Offset
Selects
Input Ready
Flag
Input Ready
Flag
Port A Mailbox
Select
Port B Mailbox
Select
Mail1 Register
Flag
Mail2 Register
Flag
Port A Data
Name
(Port A)
(Port B)
(Port A)
(Port B)
(Port A)
(Port B)
I/O
I/0
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words
in FIFO2 is less than or equal to the value in the Almost-Empty A Offset register, X2.
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words
in FIFO1 is less than or equal to the value in the Almost-Empty B Offset register, X1.
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty
36-bit bidirectional data port for side B.
CLKA is a continuous clock that synchronizes all data transfers through port A and can be
asynchronous or coincident to CLKB. IRA, ORA, AFA, and AEA are all synchronized to the
LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through port B and can be
asynchronous or coincident to CLKA. IRB, ORB, AFB, and AEB are synchronized to the LOW-
to-HIGH transition of CLKB.
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A.
The A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on
port B. The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
The LOW-to-HIGH transition of a FlFO’s Reset input latches the values of FS0 and FS1.
If either FS0 or FS1 is HIGH when a Reset goes HIGH, one of three preset values is selected as
the offset for the FlFOs Almost-Full and Almost-Empty flags. If both FIFOs are reset simultaneously
and both FS0 and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1
load the Almost-Empty and Almost-Full offsets for both FlFOs.
IRA is synchronized to the LOW-to-HIGH transition of CLKA. When IRA is LOW, FIFO1 is full
and writes to its array are disabled. IRA is set LOW when FIFO1 is reset and is set HIGH on the
second LOW-to-HIGH transition of CLKA after reset.
IRB is synchronized to the LOW-to-HIGH transition of CLKB. When IRB is LOW, FIFO2 is full
and writes to its array are disabled. IRB is set LOW when FIFO2 is reset and is set HIGH on the
second LOW-to-HIGH transition of CLKB after reset.
When the A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for
output and a LOW level selects FIFO2 output register data for output.
A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register or output and
a LOW level selects FIFO1 output register data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1
register. Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by
a LOW-to-HIGH transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is
set HIGH when FIFO1 is reset.
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.
to-HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is also
set HIGH when FIFO2 is reset.
36-bit bidirectional data port for side A.
locations in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
locations in FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
A HIGH level on MBA chooses a mailbox register for a port A read or write operation.
Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-
4
Description
COMMERCIAL TEMPERATURE RANGE