IDT723642L15PF IDT, Integrated Device Technology Inc, IDT723642L15PF Datasheet - Page 8

• Manufacturer Part Number: IDT723642L15PF
• Description: IC FIFO SYNC 2048X36 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT723642L15PF

• Function: Synchronous
• Memory Size: 72K (2K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Configuration: Dual
• Density: 72Kb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 1Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 723642L15PF

TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: V
NOTES:
1. Industrial temperature range product is available by special order.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
S
DS
DH
CLK
CLKH
CLKL
ENS1
ENS2
RSTS
FSS
ENH
RSTH
FSH
SKEW1
SKEW2
(3)
(3,4)
Clock Frequency, CLKA or CLKB
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
Pulse Duration, CLKA and CLKB LOW
Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑
Setup Time, CSA and W/RA before CLKA↑; CSB and W/RB before CLKB↑
Setup Time, ENA and MBA, before CLKA↑; ENB and MBB before CLKB↑
Setup Time, RST1 or RST2 LOW before CLKA or CLKB
Setup Time, FS0 and FS1 before RST1 and RST2 HIGH
Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB,
and MBB after CLKB↑
Hold Time, RST1 or RST2 LOW after CLKA↑ or CLKB↑
Hold Time, FS0 and FS1 after RST1 and RST2 HIGH
Skew Time, between CLKA↑ and CLKB↑ for ORA, ORB, IRA, and IRB
Skew Time, between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB
CC
= 5V ± 10%, T
A
= 0°C to +70°C)
Parameter
(2)
(2)
8
7.5
0.5
0.5
7.5
Min.
—
12
12
IDT723622L12
IDT723632L12
IDT723642L12
5
5
3
4
3
5
4
2
Max.
COMMERCIAL TEMPERATURE RANGE
83
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Commercial
Min.
4.5
4.5
7.5
7.5
—
15
12
IDT723622L15
IDT723632L15
IDT723642L15
6
6
4
5
1
1
4
2
Max.
66.7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns