IDT723642L15PF IDT, Integrated Device Technology Inc, IDT723642L15PF Datasheet - Page 10

• Manufacturer Part Number: IDT723642L15PF
• Description: IC FIFO SYNC 2048X36 120QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT723642L15PF

• Function: Synchronous
• Memory Size: 72K (2K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-TQFP, 120-VQFP
• Configuration: Dual
• Density: 72Kb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 1Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 120
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 723642L15PF

SIGNAL DESCRIPTION
RESET
providing a LOW pulse to RSTI and RST2 simultaneously. Afterwards, the FIFO
memories of the IDT723622/723632/723642 are reset separately by taking
their Reset (RST1, RST2) inputs LOW for at least four port A Clock (CLKA) and
four port B Clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can switch
asynchronously to the clocks. A FIFO reset initializes the internal read and write
pointers and forces the Input Ready flag (IRA, IRB) LOW, the Output Ready
flag (ORA, ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the Almost-
Full flag (AFA, AFB) HIGH. Resetting a FIFO also forces the Mailbox Flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a FlFO is reset, its
Input Ready flag is set HIGH after two clock cycles to begin normal operation.
the value of the Flag Select (FS0, FS1) inputs for choosing the Almost-Full and
Almost-Empty offset programming method (for details see Table 1, Flag
Programming and the Almost-Empty Flag and Almost-Full Flag Offset
Programming section that follows). The relevant FIFO Reset timing diagram can
be found in Figure 2.
ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET PRO-
GRAMMING
the Almost-Empty and Almost-Full flags. The port B Almost-Empty flag (AEB)
Offset register is labeled X1 and the port A Almost-Empty flag (AEA) Offset register
is labeled X2. The port A Almost-Full flag (AFA) Offset register is labeled Y1 and
the port B Almost-Full flag (AFB) Offset register is labeled Y2. The index of each
register name corresponds to its FIFO number. The offset registers can be
loaded with preset values during the reset of a FIFO or they can be programmed
from port A (see Table 1).
— PRESET VALUES
with one of the three preset values listed in Table 1, at least one of the flag select
inputs must be HIGH during the LOW-to-HIGH transition of its Reset input. For
example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be
HIGH when FlFO1 Reset (RST1) returns HIGH. Flag offset registers associated
with FIFO2 are loaded with one of the preset values in the same way with FIFO2
Reset (RST2) toggled simultaneously with FIFO1 Reset (RST1). For preset
value loading timing diagram, see Figure 2.
TABLE 1 — FLAG PROGRAMMING
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
FS1
After power up, a Master Reset operation must be performed by
A LOW-to-HIGH transition on a FlFO Reset (RST1, RST2) input latches
Four registers in these devices are used to hold the offset values for
To load the FIFO's Almost-Empty flag and Almost-Full flag Offset registers
H
H
H
H
L
L
L
FS0
H
H
H
H
L
L
L
RST1
↑
X
↑
X
↑
X
↑
RST2
X
↑
X
↑
X
↑
↑
X1 AND Y1 REGlSTERS(1)
Programmed from port A
10
64
16
X
X
8
X
— PARALLEL LOAD FROM PORT A
be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH
transition of the Reset inputs. After this reset is complete, the first four writes to
FIFO1 do not store data in the FIFO memory but load the offset registers in the
order Y1, X1, Y2, X2. The port A data inputs used by the offset registers are
(A7-A0), (A8-A0), or (A9-A0) for the IDT723622, IDT723632, or IDT723642,
respectively. The highest numbered input is used as the most significant bit of
the binary number in each case. Valid programming values for the registers
ranges from 1 to 252 for the IDT723622; 1 to 508 for the IDT723632; and 1 to
1,020 for the IDT723642. After all the offset registers are programmed from port
A, the port B Input Ready flag (IRB) is set HIGH, and both FIFOs begin normal
operation. See Figure 3 for relevant offset register parallel programming timing
diagram.
FIFO WRITE/READ OPERATION
Select (CSA) and port A Write/Read select (W/RA). The A0-A35 outputs are
in the high-impedance state when either CSA or W/RA is HIGH. The A0-A35
outputs are active when both CSA and W/RA are LOW.
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH , MBA is
LOW, and IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a
LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is LOW, ENA is
HIGH, MBA is LOW, and ORA is HIGH (see Table 2). FIFO reads and writes
on port A are independent of any concurrent port B operation. Write and Read
cycle timing diagrams for port A can be found in Figure 4 and 7.
that the port B Write/Read select (W/RB) is the inverse of the port A Write/Read
select (W/RA). The state of the port B data (B0-B35) outputs is controlled by the
port B Chip Select (CSB) and port B Write/Read select (W/RB). The B0-B35
outputs are in the high-impedance state when either CSB is HIGH or W/RB is
LOW. The B0-B35 outputs are active when CSB is LOW and W/RB is HIGH.
transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is LOW,
and IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a LOW-
to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH,
MBB is LOW, and ORB is HIGH (see Table 3) . FIFO reads and writes on port
B are independent of any concurrent port A operation. Write and Read cycle
timing diagrams for port B can be found in Figure 5 and 6.
To program the X1, X2, Y1, and Y2 registers from port A, both FlFOs should
The state of the port A data (A0-A35) outputs is controlled by port A Chip
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
The port B control signals are identical to those of port A with the exception
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
COMMERCIAL TEMPERATURE RANGE
X2 AND Y2 REGlSTERS(2)
Programmed from port A
64
16
X
X
X
8