IDT723642L15PF IDT, Integrated Device Technology Inc, IDT723642L15PF Datasheet - Page 22

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IDT723642L15PF

Manufacturer Part Number
IDT723642L15PF
Description
IC FIFO SYNC 2048X36 120QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet

Specifications of IDT723642L15PF

Function
Synchronous
Memory Size
72K (2K x 36)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
120-TQFP, 120-VQFP
Configuration
Dual
Density
72Kb
Access Time (max)
10ns
Word Size
36b
Organization
1Kx36x2
Sync/async
Synchronous
Expandable
No
Bus Direction
Bi-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
400mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
120
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
723642L15PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT723642L15PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT723642L15PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. t
2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT723622, 512 for the IDT723632, 1,024 for the IDT723642.
CLKB
CLKA
A0 - A35
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
B0 - B35
ENB
AFB
ENA
and rising CLKA edge is less than t
SKEW2
CLKA
CLKB
W/RA
MBF1
W/RB
MBA
CSB
MBB
CSA
ENA
ENB
is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge
[D-(Y2+1)] Words in FIFO2
t
ENS2
t
EN
SKEW2
t
t
t
t
ENS1
ENS2
ENS1
ENS2
, then AFB may transition HIGH one CLKB cycle later than shown.
FIFO1 Output Register
t
ENH
t
PAF
t
DS
Figure 15. Timing for AFB
Figure 16. Timing for Mail1 Register and MBF1
W1
t
MDV
t
t
t
t
t
ENH
DH
ENH
ENH
ENH
t
ENS2
t
PMF
t
PMR
AFB
AFB
AFB when FIFO2 is Almost-Full
AFB
22
(D-Y2) Words in FIFO2
t
SKEW2
t
ENH
W1 (Remains valid in Mail1 Register after read)
(1)
t
ENS2
MBF1
MBF1
MBF1 Flag
1
MBF1
COMMERCIAL TEMPERATURE RANGE
t
ENH
t
PMF
2
t
PAF
t
DIS
3022 drw 18
3022 drw 17

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