RTL8181 ETC, RTL8181 Datasheet - Page 47

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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Contention Window Register (WLAN_CWR)
Retry Count Register (WLAN_RETRYCTR)
Receive Descriptor Start Address Register (WLAN_RDSAR)
WEP Key mapping
The WEP key table will contain 64 entries that include the key to be used to encrypt the transmit packets and decrypted the
received frame. Each entry contains the MAC address, associated key value, key type (may be 40bits or 104 bits) and a
key- valid flag.
To set/get an entry to/from the table, you can’t access the table memory directly. Instead, the access should go through
registers because the key table is embedded in ASIC. When reading/writing the entry, you have to specify which table entry
you are going to access by an index value defined in register KeyMapIdx.
For example, if you wants to update a table entry, you need set MAC address in keyMapAddr, set key value in KeyMapKey,
specify key type (40bits or 104bits) in KeyMapType , set table index in keyMapIdx, assert the valid flag in KeyMapValid,
and write ‘1’ in KeyMapOp as ’ write’ operation. After all these values are set, you have to set ‘1’ in register KeyMapPoll bit
to tell WLAN controller to process the request. Then, you may wait the WLAN controller to accomplish the operation by
polling KeyMapPoll bit until it is cleared.
There is no default value for these registers in initialization. Therefore, you have to reset the KeyMapValid flag for those
entries you did not used.
Key Map MAC Address (WLAN_KMAR)
Bit
47-0
Key Map Key Value (WLAN_KMKEY)
Bit
127-0
Key Map Config (WLAN_KMC)
Bit
15-10
9-8
7
CONFIDENTIAL
3
2
1
0
Bit
15-10
9-0
Bit
7-0
Bit
31-0
SBQ
SHPQ
SNPQ
SLPQ
Bit Name
-
CW
Bit Name
RetryCT
Bit Name
RDSA
Bit Name
KeyMapAddr MAC address
Bit Name
KeyMapKey WEP key value
Bit Name
KeyMapIdx
KeyMapType Key value type. 0 – 40bits, 1-104bits, 2-3 reserved.
KeyMapValid Valid flag. If this bit is ‘1’, it indicates the table entry, indexed by KeyMapIdx, is valid. Bit
Description
Reserved
Contention Window: This register indicates the number of contention windows before
transmitting a packet.
Description
Retry Count: This register indicates the number of retry counts when a packet transmit is
completed.
Description
Receive Descriptor Start Address: This is a 32-bit address.
Description
Description
Description
Key map index, specify which table entry to read or write.
Stop Beacon Queue: Write a 1 to this bit by software to notify the RTL8181 to stop the
DMA mechanism of the Beacon Queue. This bit is invalid when DPS (bit3, Config 2) is set
to 1.
Stop High Priority Queue: Write a 1 to this bit by software to notify the RTL8181 to stop
the DMA mechanism of the High Priority Queue.
Stop Normal Priority Queue: Write a 1 to this bit by software to notify the RTL8181 to stop
the DMA mechanism of the Normal Priority Queue. This bit is invalid when DPS (bit3,
Config 2) is set to 1.
Stop Low Priority Queue: Write a 1 to this bit by software to notify the RTL8181 to stop the
DMA mechanism of the Low Priority Queue.
47
RTL8181
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
R/W
-
R
R/W
R
R/W
R/W
v1.0