RTL8181 ETC, RTL8181 Datasheet - Page 31

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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0xBD01_00D7
0xBD01_00DB 1
0xBD01_00DF
Interrupt Enable Register (UART_IER)
Bit
7-6
5
3
4
2
1
0
Interrupt Identification Register (UART_IIR)
Bit
7:5
4
3:1
0
Interrupt Priority
Interrupt
Identification Register
Bit3 Bit2 Bit1 Bit0
0
0
0
1
0
0
FIFO Control Register (UART_FCR)
Bit
7-6
3-5
2
1
0
CONFIDENTIAL
0
1
1
1
0
0
Bit Name
-
ELP
EDSSI
ESLP
ELSI
ETBEI
ERBI
Bit Name
FIFO64[2:0]
-
IID[2:0]
IPND
Bit Name
RTRG[1:0]
-
TFRST
RFRST
EFIFO
0
1
0
0
1
0
1
1
1
0
0
0
0
0
Priority
level
None
1
2
2
3
4
Description
Reserved
Low power mode enable
Enable modem status registe r interrupt
Sleep mode enable
Enable receiver line status interrupt
Enable transmitter holding register empty interrupt R/W
Enable received data available interrupt
Description
000 = no FIFO
110 = 16-byte FIFO
Reserved
Interrupt ID. IID[1:0] indicates the interrupt
priority.
Interrupt pending
0 = interrupt pending
Description
Receiver trigger level
Trigger level: 16-byte
00 = 01
01 = 04
10 = 08
11 = 14
Reserved
Transmitter FIFO reset. Writes 1 to clear the
transmitter FIFO.
Receiver FIFO reset. Writes 1 to clear the receiver
FIFO.
Enable FIFO. When this bit is set, enable the
UART_LSR
UART_MSR Modem status register
UART_SCR
Interrupt type
None
Receiver line
status
Received data
available
Character
time-out
indication
Transmitter
holding register
empty
Modem status
Line status register
Scratch register
Interrupt source
None
Overrun, parity, framing
errors or break
DR bit is set.
No characters have been
removed from or input to
FIFO during the last character
times and at 1 character in it.
THRE bit set.
CTS#,DSR#,RI#,DCD#
31
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R/W
W
W
W
W
Interrupt reset
method
None
Read LSR
Read RBR.
Read RBR
Reading IIR or write
THR
Reading MSR
InitVal
0
0
0
0
0
0
InitVal
110
0
000
0
InitVal
11
0
0
0
R/W
R/W
R/W
RTL8181
v1.0