RTL8181 ETC, RTL8181 Datasheet - Page 30

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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0
0
0
0
0
0
0
0
0
0
0
4
4
4
8
9. UART Controller
RTL8181 provides a 16C550 compatible UART, which contains 16 byte FIFOs. In addition, auto flow control is provided, in
which, auto-CTS mode (CTS controls transmitter) and auto-RTS mode (Receiver FIFO contents and threshold control RTS)
are both supported. The baud rate is programmable and allows division of any input reference clock by 1 to (2^16-1) and
generates an internal 16x clock. RTL8181 provides fully programmable serial interface, which can be configured to support
7,8 bit characters, even, odd, no parity generation and detection, and 1 or 2 stop bit generation. Last, full y prioritized interrupt
control and loopback functionality for diagnostic capability are also provided.
The clock source is 22MHz.
UART Register Set
Virtual address Size (byte) Name
0xBD01_00C3
0xBD01_00C3
0xBD01_00C3
0xBD01_00C7
0xBD01_00C7
0xBD01_00CB
0xBD01_00CB 1
0xBD01_00CF
0xBD01_00D3
CONFIDENTIAL
23
22
21
20
19
18
17-16 PDI[1:0] Protocol ID1, Protocol ID0
15
14
13
12-0 Frame_Le
31-17 RSEV
16
15-0 VLAN_T
31-0 RxBuff
BOVF
FOVF
RWT
RES
RUNT
CRC
IPF
UDPF
TCPF
ngth
TAVA
AG
1
1
1
1
1
1
1
1
Buffer Overflow. When set, indicates that receive buffer has ever
exhausted before this packet is received.
FIFO Overflow. When set, indicates that FIFO overflow has ever
occurred before this packet is received.
Receive Watchdog Timer expired. When set, indicates that the received
packet length exceeds 1724 bytes, the receive watchdog timer will
expire and stop receive engine.
Receive Error Summary. When set, indicates at least one of the
following errors occurred: CRC, RUNT, RWT, FAE. This bit is valid
only when LS(Last segment bit) is set
Runt packet. When set, indicates that the received packet length is
smaller than 64 bytes. RUNT packet is able to be received only when
RCR_AR is set.
CRC error. When set, indicates that a CRC error has occurred on the
received packet. A CRC-error packet can be received only when
RCR_AER is set.
00: Non-IP
01: TCP/IP
10: UDP/IP
11: IP.
When set, indicates IP checksum failure.
When set, indicates UDP checksum failure.
When set, indicates TCP checksum failure.
When OWN=0 and LS =1, it indicates the received packet length
including CRC, in bytes.
Reserved.
Tag Available. When set, the received packet is an IEEE802.1Q VLAN
TAG (0x8100) available packet.
If the packet ‘s TAG is 0x8100, The NIC extrac ts four bytes from after
source ID, sets TAVA bit to1, and moves the TAG value to this field in
Rx descriptor.
Logic Address of receive buffer.
UART_RBR
UART_THR
UART_DLL
UART_IER
UART_DLM Divisor latch MSB. (DLAB=1)
UART_IIR
UART_FCR
UART_LCR
UART_MCR Modem control register
Description
Receiver buffer register. (DLAB=0)
Transmitter holding register. (DLAB=0)
Divisor latch LSB. (DLAB=1)
Interrupt enable register. (DLAB=0)
Interrupt identification register.
FIFO control register
Line control register
30
Access
R
W
R/W
R/W
R/W
R
W
R/W
R/W
RTL8181
v1.0