RTL8181 ETC, RTL8181 Datasheet - Page 10

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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PAPE
PE1/PHIT
XQ
PE2
RXIP
RXIN
RXQP
RXQN
RSSI
TXDET
VREFI
TXIP
TXIN
TXQP
TXQN
TXAGC
RXAGC
Miscellaneous
R10K
XO
XI
PCI Interface
AD31-0
C/BE3-0
CLK
DEVSELB S/T/
FRAMEB S/T/
GNTB
REQB
IDSEL
INTAB
IRDYB
CONFIDENTIAL
O
O
O
AI* 110
X
AI
X
X
AI
AI
AO 97
AO 96
AO 94
AO 93
AO 91
AO 90
I/O
O
I
T/S *X
T/S *X
O
S
S
T/S *X
T/S *X
O
O/D *X
S/T/
S
*X
*X
*X
*X
*X
82
84
85
109
106
105
103
102
101
99
87
88
K19
K18
J20
B19
B20
C18
C19
D17
D18
C20
E19
F18
E20
F20
F19
G18
E18
H18
H19
A13,B12,A8
,C8,B8,C4,
B3,A3,C2,D
3,C1,G1,H3,
J3,V2,V1,V
3,W2,V4,w
3,Y3,W6,Y
6,V7,Y14,
W14,Y15,Y
19,U16,R18
,T20,R19
W20,V19,U
17,V20
N19
P3
N20
H20
J18
A16
A17
M18
Transmit PA Power Enable: Assert high when starting transmission.
Not used in the Maxim RF chipset.
Not used in the Maxim RF chipset now.
Receive (Rx) In-phase Analog Data: Positive path of differential pair.
Receive (Rx) In-phase Analog Data: Negative path of differential pair.
Receive (Rx) Quadrature-phase Analog Data: Positive path of differential pair.
Receive (Rx) Quadrature-phase Analog Data: negative path of differential pair.
Not used in Maxim RF chipset.
To internal ADC which detects transmit power.
Not used in Maxim RF chipset.
Transmit (TX) In-phase Digital Data: Combining before connecting to TX_I of
RF2948B.
Transmit (TX) Quadrature Digital Data: Combining before connecting to TX_Q
of RF2948B.
Transmit gain control output to RF2948.
Analog Drive to the Receive r AGC Control.
This pin must be pulled low by a 10K O resistor.
Crystal Feedback Output: This output is reserved for crystal connection. It should
be left open when XI is driven with an external 44 MHz oscillator.
44 MHz OSC Input
PCI address and data multiplexed pins. The address phase is the first clock cycle in
which FRAMEB is asserted. During the address phase, AD31-0 contains a physical
address (32 bits). For I/O, this is a byte address, and for configuration and memory, it
is a double-word address. Write data is stable and valid when IRDYB is asserted. Read
data is stable and valid when TRDYB is asserted. Data I is transferred during those
clocks where both IRDYB and TRDYB are asserted.
PCI bus command and byte enables multiplexed pins. During the address phase
of a transaction, C/BE3-0 define the bus command. During the data phase,
C/BE3-0 are used as Byte Enables. The Byte Enables are valid for the entire data
phase and determine which byte lanes carry meaningful data. C/BE0 applies to
byte 0, and C/BE3 applies to byte 3.
PCI clock: This clock input provides timing for all PCI transactions and is input
to the PCI device.
Device Select: As a bus master, the RTL8181 samples this signal to insure that a
PCI target recognizes the destination address for the data transfer.
Cycle Frame: As a bus master, this pin indicates the beginning and duration of an
access. FRAMEB is asserted low to indicate the start of a bus transaction. While
FRAMEB is asserted, data transfer continues. When FRAMEB is deasserted, the
transaction is in the final data phase.
As a target, the device monitors this signal before decoding the address to check
if the current transaction is addressed to it.
Grant:Grant indicate to the agent that access to the bus has been granted.
Request: Request indicates to the ar biter that this agent desires use of the bus.
Initialization Device Select: This pin is used as a chip select during configuration
read and write transactions..
Interrupt A: Used to request an interrupt. It is asserted low when an interrupt
condition occurs, as defined by the Interrupt Status, Interrupt Mask.
Initiator Ready: This indicates the initiating agent’s ability to complete the
current data phase of the transaction.
As a bus master, this signal will be asserted low when the RTL8181 is ready to
10
RTL8181
v1.0