RTL8181 ETC, RTL8181 Datasheet - Page 40

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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3
2
1
0
Interrupt Status Register (WLAN_ISR)
This register indicates the source of WLAN controller interrupt goes active. Enabling the corresponding bits in the Interrupt
Mask Register (WLAN_IMR) allows bits in this register to produce an interrupt. When an interrupt is active, one of more bits
in this register are set to a “1”. The interrupt Status Register reflects all current pending interrupts, regardless of the state of the
corresponding mask bit in the WLAN_IMR. Reading the WLAN_ISR clears all interrupts. Writing a 1 to any bit in this
register will reset that bit.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CONFIDENTIAL
TLPDER
TLPDOK
RER
ROK
Symbol
TXFOVW
TimeOut
BcnInt
ATIMInt
TBDER
TBDOK
THPDER
THPDOK
TNPDER
TNPDOK
FOVW
_RDU
TLPDER
TLPDOK
RER
ROK
1: Enable
0: Disable
Tx Low Priority Descrip tor Error Interrupt:
1: Enable
0: Disable
Tx Low Priority Descriptor OK Interrupt:
1: Enable
0: Disable
Rx Error Interrupt:
1: Enable
0: Disable
Rx OK Interrupt:
1: Enable
0: Disable
Description
Tx FIFO Overflow
Time Out: This bit is set to 1 when the least 32 bits of the TSFTR register reaches to the
value of the TimerInt register.
Beacon Time Out Interrupt: When set, this bit indicates that the TBTT (Target Beacon
Transmission Time) has been reached after the value of the Beacon interrupt Interval
register.
ATIM Time Out Interrupt: When set, this bit indicates that the ATIM window has been gone
after the value of the Beacon interrupt Interval register.
Transmit Beacon Priority Descriptor Error: Indicates that a packet of beacon priority descriptor
transmission was aborted due to an Rx beacon frame.
Transmit Be acon Priority Descriptor OK: Indicates that a packet of beacon priority
descriptor exchange sequence has been successfully completed.
Transmit High Priority Descriptor Error: Indicates that a packet of high priority descriptor
transmission was aborted due to an SSRC (Station Short Retry Count) has reached SRL
(Short Retry Limit), and an SLRC (Station Long Retry Count) has reached LRL (Long Retry
Limit).
Transmit High Priority Descriptor OK: Indicates that a packet of high priority descriptor
exchange sequence has been successfully completed.
Transmit Normal Priority Descriptor Error: Indicates that a packet of normal priority
descriptor transmission was aborted due to an SSRC (Station Short Retry Count) has
reached SRL (Short Retry Limit), and an SLRC (Station Long Retry Count) has reached
LRL (Long Retry Limit).
Transmit Normal Priority Descriptor OK: Indicates that a packet of normal priority
descriptor exchange sequence has been successfully completed.
Rx FIFO Overflow: This bit set to 1 is caused by RDU, poor PCI performance, or
overloaded PCI traffic.
Rx Descriptor Unavailable: When set, this bit indicates that the Rx descriptor is currently
unavailable.
Transmit Low Priority Descriptor Error: Indicates that a packet of low priority descriptor
transmission was aborted due to an SSRC (Station Short Retry Count) has reached SRL
(Short Retry Limit), and an SLRC (Station Long Retry Count) has reached LRL (Long Retry
Limit).
Transmit Low Priority Descriptor OK: Indicates that a packet of low priority descriptor
exchange sequence has been successfully completed.
Receive Error: Indicates that a packet has a CRC32 or ICV error.
Receive OK: In normal mode, indicates the successful completion of a packet reception.
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RTL8181
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