RTL8181 ETC, RTL8181 Datasheet - Page 33

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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7
6
5
4
3-1
0
10. Timer & Watchdog
There are four sets of hardware timer and one watchdog timer. Each timer can be configured as timer mode or counter mode.
No matter counter or timer mode, the time value will be counted down from initial value to zero, which value is subtracted by
one in every timer clock. When configured as timer mode, the source of timer clock could be configured to use base clock
directly, or based on the base clock divided by a configurable register value – CDBR, which way is called as Basic timer.
When the value is reaching to zero, the timer is stopped and an interrupt will be issued in counter mode. If configured as timer
mode, beside to issue an interrupt, the time value will be reset to its initial value, and then count down timer be operated
continuously, and an interrupt will be issued periodically whenever the count down value reaches to zero.
When watchdog timer is enabled, it will cause the system reset when time out occurred. The time out interval could be selected
from register, the time unit value is based on base clock divided by the base value, which is same used by timer.
Timer & Watchdog Register Set
Virtual address Size (byte) Name
0xBD01_0050
0xBD01_0054
0xBD01_0058
0xBD01_005C
0xBD01_0060
0xBD01_0064
0xBD01_0068
0xBD01_006C
0xBD01_0070
0xBD01_0074
0xBD01_0078
0xBD01_007C
Timer/Counter 0 Data register (TC0CNT)
Bit
23-0
Timer/Counter 1 Data register (TC1CNT)
Bit
23-0
Timer/Counter 2 Data register (TC2CNT)
Bit
31-0
CONFIDENTIAL
DCD
RI
DSR
CTS
-
Bit Name
TC0Value[23:0] The timer or counter initial value
Bit Name
TC1Value[23:0] The timer or counter initial value
Bit Name
TC2Value[31:0] The timer or counter initial value
CTS
2
1
1
2
3
3
4
4
3
3
4
4
In loopback mode, returns the bit 2 of MCR.
In normal mode, returns 1.
In loopback mode, returns the bit 3 of MCR.
In normal mode, returns 0.
In loopback mode, returns the bit 0 of MCR
In normal mode, returns 1.
Clear to send.
0 = CTS# detected high
1 = CTS# detected low
Reserved
Delta clear to send. CTS# signal transits.
Description
Description
Description
TCCNR
TCIR
CBDR
WDTCNR Watchdog timer control register
TC0DATA Timer/Counter 0 data register. It specifies the
TC1DATA Timer/Counter 1 data register. It specifies the
TC2DATA Timer/Counter 2 data register. It specifies the
TC3DATA Timer/Counter 3 data registe r. It specifies the
TC0CNT
TC1CNT
TC2CNT
TC3CNT
Description
Timer/Counter control register
Timer/Counter interrupt register
Clock division base register
time-out duration.
time-out duration.
time-out duration.
time-out duration.
Timer/Counter 0 count register
Timer/Counter 1 count register
Timer/Counter 2 count register
Timer/Counter 3 count register
33
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
0
InitVal
InitVal
InitVal
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
RTL8181
v1.0