RTL8181 ETC, RTL8181 Datasheet - Page 32

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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Line Control Register (UART_LCR)
Bit
7
6
5-4
3
2
1-0
Modem Control Register (UART_MCR)
Bit
7-6
5
4
2-3
1
0
Line Status Register (UART_LSR)
Bit
7
6
5
4
3
2
1
0
Modem Status Register (UART_MSR)
Bit
CONFIDENTIAL
Bit Name
DLAB
BRK
EPS[1:0]
PEN
STB
WLS[1:0]
Bit Name
-
AFE
LOOP
-
RTS
-
Bit Name
RFE
TEMT
THRE
BI
FE
PE
OE
DR
Bit Name
transmitter and receiver FIFOs. Changing this bit
clears the FIFOs.
Description
Divisor latch access bit.
Break control. Set this bit force TXD to the
spacing (low) state.(break) Clear this bit to disable
break condition.
Even parity select
00 = odd parity
01 = even parity
10 = mark parity
11 = space parity
Parity enable
Number of stop bits
0 = 1 bit
1 = 2 bits
Word length select
10 = 7 bits
11 = 8 bits
Description
Reserved
Auto flow control enable
Loopback
Reserved
Request to send
0 = Set RTS# high
1 = Set RTS# low
Reserved
Description
Errors in receiver FIFO. At least one parity,
framing and break error in the FIFO.
Transmitter empty
Character mode: both THR and TSR are empty.
FIFO mode: both transmitter FIFO and TSR are
empty
Transmitter holding register empty.
Character mode: THR is empty.
FIFO mode: transmitter FIFO is empty
Break interrupt indicator
Framing error
Parity error
Overrun error. An overrun occurs when the
receiver FIFO is full and the next character is
completely received in the receiver shift register.
An OE is indicated. The character in the shift
register will be overwritten.
Data ready.
Character mode: data ready in RBR
FIFO mode: receiver FIFO is not empty.
Description
32
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R/W
InitVal
0
0
0
0
0
11
InitVal
0
0
0
InitVal
0
0
0
0
0
0
0
0
InitVal
RTL8181
v1.0