RTL8181 ETC, RTL8181 Datasheet - Page 39

• Manufacturer Part Number: RTL8181
• Description: Wireless LAN Access Point/Gateway Controller
• Manufacturer: ETC

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Bit
7:5
4
3
2
1-0
Interrupt Mask Register (WLAN_IMR)
This register masks the interrupts that can be generated from the Interrupt Status Register. A hardware reset will clear all mask
bits. Setting a mask bit allows the corresponding bit in the Interrupt Status Register to cause an interrupt. The Interrupt Status
Register bits are always set to 1 if the condition is present, regardless of the state of the corresponding mask bit.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
CONFIDENTIAL
Bit Name
-
RST
RE
TE
-
Bit Name
TXFOVW
TimeOut
BcnInt
ATIMInt
TBDER
TBDOK
THPDER
THPDOK
TNPDER
TNPDOK
RXFOVW
RDU
Description
Reserved
Reset: Setting this bit to 1 forces the RTL8181 do the WLAN MAC reset. During reset
reset state, it will disable the transmitter and receiver, and reinitializes the FIFOs. The
values of WLAN_IDR and WLAN_MAR7 will have no changes. This bit is 1 during the
reset operation, and is cleared to 0 when the reset operation is complete.
Receiver Enable: When set to 1, and the receive state machine is idle, the receive machine
becomes active. This bit will read back as 1 whenever the receive state machine is active.
After initial power- up, software must insure that the receiver has completely reset before
setting this bit.
1: Enable
0: Disable
Transmitter Enable: When set to 1, and the transmit state machine is idle, the transmit state
machine becomes active. This bit will read back as 1 whenever the transmit state machine
is active. After initial power-up, software must insure that the transmitter has completely
reset before setting this bit.
1: Enable
0: Disable
Reserved
Description
Tx FIFO Overflow Interrupt:
1: Enable
0: Disable
Time Out Interrupt:
1: Enable
0: Disable
Beacon Time out Interrupt:
1: Enable
0: Disable
ATIM Time Out Interrupt:
1: Enable
0: Disable
Tx Beacon Descriptor Error Interrupt:
1: Enable
0: Disable
Tx Beacon Descriptor OK Interrupt:
1: Enable
0: Disable
Tx High Priority Descriptor Error Interrupt:
1: Enable
0: Disable
Tx High Priority Descriptor OK Interrupt:
1: Enable
0: Disable
Tx Normal Priority Descriptor Error Interrupt:
1: Enable
0: Disable
Tx Normal Priority Descriptor OK Interrupt:
1: Enable
0: Disable
Rx FIFO Overflow Interrupt:
1: Enable
0: Disable
Rx Descriptor Unavailable Interrupt:
39
RTL8181
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
v1.0