AD7711A Analog Devices, AD7711A Datasheet - Page 8

• Manufacturer Part Number: AD7711A
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with RTD Current Source
• Manufacturer: Analog Devices

Specifications of AD7711A

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip (Vref)/(PGA Gain),Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

AD7711A
Pin
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The end-
points of the transfer function are zero scale (not to be confused
with bipolar zero), a point 0.5 LSB below the first code transition
(000 . . . 000 to 000 . . . 001) and full scale, a point 0.5 LSB
above the last code transition (111 . . . 110 to 111 . . . 111). The
error is expressed as a percentage of full scale.
Positive Full-Scale Error
Positive full-scale error is the deviation of the last code transi-
tion (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage
(AIN(–) + V
and bipolar analog input ranges.
Unipolar Offset Error
Unipolar offset error is the deviation of the first code transition
from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-
ating in the unipolar mode.
Bipolar Zero Error
This is the deviation of the midscale transition (0111 . . . 111
to 1000 . . . 000) from the ideal AIN(+) voltage (AIN(–)
– 0.5 LSB) when operating in the bipolar mode.
Bipolar Negative Full-Scale Error
This is the deviation of the first code transition from the ideal
AIN(+) voltage (AIN(–) – V
ing in the bipolar mode.
20
21
22
23
24
19
Mnemonic
TFS
RFS
DRDY
SDATA
DV
DGND
DD
REF
/GAIN – 3/2 LSBs). It applies to both unipolar
Function
Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial data
expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active after
TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data-word is written
to the part.
Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the
self-clocking mode, both the SCLK and SDATA lines become active after RFS goes low. In the external
clocking mode, the SDATA line becomes active after RFS goes low.
Logic Output. A falling edge indicates that a new output word is available for transmission. The DRDY pin
will return high upon completion of transmission of a full output word. DRDY is also used to indicate when
the AD7711A has completed its on-chip calibration sequence.
Serial Data. Input/output with serial data being written to either the control register or the calibration
registers and serial data being accessed from the control register, calibration registers, or the data register.
During an output data read operation, serial data becomes active after RFS goes low (provided DRDY is low).
During a write operation, valid serial data is expected on the rising edges of SCLK when TFS is low. The
output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs.
Digital Supply Voltage, 5 V. DV
Ground Reference Point for Digital Circuitry.
REF
/GAIN + 0.5 LSB) when operat-
DD
should not exceed AV
–8–
Positive Full-Scale Overrange
Positive full-scale overrange is the amount of overhead available
to handle input voltages on AIN(+) input greater than AIN(–) +
V
system gain errors in system calibration routines) without intro-
ducing errors due to overloading the analog modulator or over-
flowing the digital filter.
Negative Full-Scale Overrange
This is the amount of overhead available to handle voltages on
AIN(+) below AIN(–) – V
analog modulator or overflowing the digital filter. Note that the
analog input will accept negative voltage peaks even in the uni-
polar mode provided that AIN(+) is greater than AIN(–) and
greater than V
Offset Calibration Range
In the system calibration modes, the AD7711A calibrates its
offset with respect to the analog input. The offset calibration
range specification defines the range of voltages that the
AD7711A can accept and still accurately calibrate offset.
Full-Scale Calibration Range
This is the range of voltages that the AD7711A can accept in
the system calibration mode and still correctly calibrate full scale.
Input Span
In system calibration schemes, two voltages applied in sequence
to the AD7711A’s analog input define the analog input range.
The input span specification defines the minimum and maxi-
mum input voltages from zero scale to full scale that the AD7711A
can accept and still calibrate accurately gain.
REF
/GAIN (for example, noise peaks or excess voltages due to
DD
by more than 0.3 V in normal operation.
SS
– 30 mV.
REF
/GAIN without overloading the
REV. D