AD7711A Analog Devices, AD7711A Datasheet - Page 2

• Manufacturer Part Number: AD7711A
• Description: CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with RTD Current Source
• Manufacturer: Analog Devices

Specifications of AD7711A

• Resolution (bits): 24bit
• # Chan: 2
• Sample Rate: 19.5kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip (Vref)/(PGA Gain),Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

AD7711A–SPECIFICATIONS
REF IN(–) = AGND; MCLK IN = 10 MHz, unless otherwise stated. All specifications T
Parameter
STATIC PERFORMANCE
ANALOG INPUTS/REFERENCE INPUTS
REFERENCE OUTPUT
NOTES
10
11
1
2
3
4
5
6
7
8
9
V
The reference input voltage range may be restricted by the input voltage range requirement on the V
Temperature ranges are as follows: A Version, –40∞C to +85∞C; S Version, –55∞C to +125∞C.
Applies after calibration at the temperature of interest.
Positive full-scale error applies to both unipolar and bipolar input ranges.
These errors will be of the order of the output noise of the part as shown in Table I when using system calibration. These errors are 20 mV typical when using self-
calibration or background calibration.
Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
This common-mode voltage range is allowed, provided that the input voltage on AIN(+) and AIN(–) does not exceed AV
These numbers are guaranteed by design and/or characterization.
The analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recommended source
resistance depends on the selected gain (see Tables IV and V).
The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs. The absolute
voltage on the analog inputs should not go more positive than AV
No Missing Codes
Output Noise
Integral Nonlinearity @ 25∞C
Positive Full-Scale Error
Full-Scale Drift
Unipolar Offset Error
Unipolar Offset Drift
Bipolar Zero Error
Bipolar Zero Drift
Gain Drift
Bipolar Negative Full-Scale Error
Bipolar Negative Full-Scale Drift
Common-Mode Rejection (CMR)
Common-Mode Voltage Range
Normal-Mode 50 Hz Rejection
Normal-Mode 60 Hz Rejection
Common-Mode 50 Hz Rejection
Common-Mode 60 Hz Rejection
DC Input Leakage Current
Sampling Capacitance
Analog Inputs
Reference Inputs
Output Voltage
Initial Tolerance @ 25∞C
Drift
Output Noise
Line Regulation (AV
Load Regulation
External Current
REF
T
T
T
Input Voltage Range
Input Sampling Rate, f
REF IN(+) – REF IN(–) Voltage
Input Sampling Rate, f
= REF IN(+) – REF IN(–).
MIN
MIN
MIN
to T
to T
to T
MAX
MAX
MAX
8
5
5
2, 4
DD
5
2, 4
7
9
)
2, 3, 4
S
S
7
@ 25∞C
6
7
7
5
7
7
2
@ 25∞C
11
24
20
A, S Versions
22
18
15
12
See Tables I and II
± 0.0015
0.003
1
0.3
0.5
0.25
0.5
0.25
2
± 0.003
± 0.006
1
0.3
100
90
V
100
100
150
150
10
1
20
0 to +V
± V
See Table III
2.5 to 5
f
2.5
± 1
30
1
1.5
1
CLK IN
SS
REF
to AV
/256
REF
DD
10
DD
(AV
1
+ 30 mV or go more negative than V
DD
= +5 V
Unit
Bits min
Bits min
Bits min
Bits min
Bits min
% FSR max
% FSR max
mV/∞C typ
mV/∞C typ
mV/∞C typ
mV/∞C typ
mV/∞C typ
mV/∞C typ
ppm/∞C typ
% FSR max
% FSR max
mV/∞C typ
mV/∞C typ
dB min
dB min
V min to V max
dB min
dB min
dB min
dB min
pA max
nA max
pF max
nom
nom
V min to V max
V nom
% max
ppm/∞C typ
mV typ
mV/V max
mV/mA max
mA max
–2–
5%; DV
DD
MIN
= +5 V
to T
BIAS
Conditions/Comments
Guaranteed by Design. For Filter Notches £ 60 Hz
For Filter Notch = 100 Hz
For Filter Notch = 250 Hz
For Filter Notch = 500 Hz
For Filter Notch = 1 kHz
Depends on Filter Cutoffs and Selected Gain
Filter Notches £ 60 Hz
Typically ± 0.0003%
Excluding Reference
Excluding Reference. For Gains of 1, 2
Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
For Gains of 1, 2
For Gains of 4, 8, 16, 32, 64, 128
Excluding Reference
Typically ± 0.0006%
Excluding Reference. For Gains of 1, 2
Excluding Reference. For Gains of 4, 8, 16, 32, 64, 128
At dc and AV
At dc and AV
For Filter Notches of 10, 25, 50 Hz, ± 0.02 ¥ f
For Filter Notches of 10, 30, 60 Hz, ± 0.02 ¥ f
For Filter Notches of 10, 25, 50 Hz, ± 0.02 ¥ f
For Filter Notches of 10, 30, 60 Hz, ± 0.02 ¥ f
For Normal Operation. Depends on Gain Selected
Unipolar Input Range (B/U Bit of Control Register = 1)
Bipolar Input Range (B/U Bit of Control Register = 0)
For Specified Performance. Part Functions with
Lower V
pk-pk Noise 0.1 Hz to 10 Hz Bandwidth
Maximum Load Current 1 mA
MAX
input.
SS
, unless otherwise noted.)
– 30 mV.
5%; V
REF
Voltages
SS
DD
DD
= 0 V or –5 V
= 5 V
= 10 V
DD
+ 30 mV and V
5%; REF IN(+) = +2.5 V;
SS
– 30 mV.
NOTCH
NOTCH
NOTCH
NOTCH
REV. D